9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer 9DBU0931 DATASHEET Description Features/Benefits The 9DBU0931 is a member of IDT s 1.5V Ultra-Low-Power LP-HCSL outputs save 18 resistors compared to standard (ULP) PCIe family. The device has 9 output enables for clock HCSL outputs management, and 3 selectable SMBus addresses. 47mW typical power consumption in PLL mode minimal power consumption Recommended Application Outputs can optionally be supplied from any voltage 1.5V PCIe Gen1-2-3 Fanout Buffer (FOB) between 1.05 and 1.5V maximum power savings Spread Spectrum (SS) compatible allows SS for EMI Output Features reduction 9 1167MHz Low-Power (LP) HCSL DIF pairs OE pins for each output support DIF power management HCSL-compatible differential input can be driven by Key Specifications common clock sources DIF additive cycle-to-cycle jitter < 5ps SMBus-selectable features optimize signal integrity to DIF output-to-output skew < 60ps application DIF additive phase jitter is < 300fs rms for PCIe Gen 3 slew rate for each output DIF additive phase jitter < 350fs rms for SGMII differential output amplitude Device contains default configuration SMBus interface not required for device operation 3.3V tolerant SMBus interface works with legacy controllers Three selectable SMBus addresses multiple devices can easily share an SMBus segment 6 6 mm 48-VFQFPN minimal board space Block Diagram vOE(8:0) 9 DIF8 DIF7 DIF6 CLK IN DIF5 CLK IN DIF4 vSADR DIF3 DIF2 CKPWRGD PD CONTROL LOGIC SDATA 3.3 DIF1 SCLK 3.3 DIF0 9DBU0931 MARCH 9, 2017 1 2017 Integrated Device Technology, Inc.9DBU0931 DATASHEET Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 vSADR tri 1 36 DIF5 vOE8 2 35 DIF5 DIF8 3 34 vOE4 DIF8 4 33 DIF4 VDDR1.5 5 32 DIF4 CLK IN 6 31 VDDIO 9DBU0931 CLK IN 7 30 VDDO1.5 epad is GND GNDR 8 29 GND GNDDIG 9 28 vOE3 SCLK 3.3 10 27 DIF3 SDATA 3.311 26DIF3 VDDDIG1.512 25vOE2 13 14 15 16 17 18 19 20 21 22 23 24 48-pin VFQFPN, 6x6 mm, 0.4mm pitch v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor prefix indicates internal 120KOhm pull up resistor SMBus Address Selection Table + Read/Write bit SADR Address 0 1101011 x State of SADR on first application of M 1101100 x CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin OEx bit True O/P Comp. O/P 0X X X Low Low 1 Running 0 X Low Low 1 Running 1 0 Running Running 1 Running 1 1 Low Low Power Connections Pin Number Description VDD VDDIO GND Input 58 receiver analog 12 9 Digital power 20,30,31,38 13,21,31,39,47 22,29,40 DIF outputs Note: EPAD on this device is not electrically connected to the die. It should be connected to ground for best thermal performance. 9-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER 2 MARCH 9, 2017 VDDIO CKPWRGD PD vOE0 VDDIO DIF0 vOE7 DIF0 DIF7 vOE1 DIF7 DIF1 vOE6 DIF1 DIF6 VDD1.5 DIF6 VDDIO GND GND VDDIO DIF2 VDD1.5 DIF2 vOE5