9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer 9DBU0941 with Zo=100ohms DATASHEET Description Features/Benefits The 9DBU0941 is a member of IDT s 1.5V Ultra-Low-Power Direct connection to 100 transmission lines save 36 (ULP) PCIe family. It has integrated terminations for direct resistors compared to standard HCSL outputs connection to 100 transmission lines. The device has 9 47mW typical power consumption eliminates thermal output enables for clock management, and 3 selectable concerns SMBus addresses. Outputs can optionally be supplied from any voltage between 1.05 and 1.5V maximum power savings Recommended Application Spread Spectrum (SS) compatible allows SS for EMI 1.5V PCIe Gen1-2-3 Fanout Buffer (FOB) reduction OE pins for each output support DIF power management Output Features HCSL-compatible differential input can be driven by 9 1167MHz Low-Power (LP) HCSL DIF pairs with common clock sources ZO=100 SMBus-selectable features optimize signal integrity to application Key Specifications slew rate for each output DIF additive cycle-to-cycle jitter < 5ps differential output amplitude DIF output-to-output skew < 60ps Device contains default configuration SMBus interface not DIF additive phase jitter is < 300fs rms for PCIe Gen3 required for device operation DIF additive phase jitter < 350s rms for SGMII Selectable SMBus addresses multiple devices can easily share an SMBus segment 3.3V tolerant SMBus interface works with legacy controllers 6 6 mm 48-VFQFPN minimal board space Block Diagram vOE(8:0) 9 DIF8 DIF7 DIF6 CLK IN DIF5 CLK IN DIF4 vSADR DIF3 DIF2 CKPWRGD PD CONTROL LOGIC SDATA 3.3 DIF1 SCLK 3.3 DIF0 9DBU0941 MARCH 9, 2017 1 2017 Integrated Device Technology, Inc.9DBU0941 DATASHEET Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 vSADR tri 1 36 DIF5 vOE8 2 35 DIF5 DIF8 3 34 vOE4 DIF8 4 33 DIF4 VDDR1.5 5 32 DIF4 CLK IN 6 31 VDDIO 9DBU0941 CLK IN 7 30 VDDO1.5 epad is GND GNDR 8 29 GND GNDDIG 9 28 vOE3 SCLK 3.3 10 27 DIF3 SDATA 3.3 11 26 DIF3 VDDDIG1.5 12 25 vOE2 13 14 15 16 17 18 19 20 21 22 23 24 48-pin VFQFPN, 6x6 mm, 0.4mm pitch v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor prefix indicates internal 120KOhm pull up resistor SMBus Address Selection Table + Read/Write bit SADR Address 0 1101011 x State of SADR on first application of M 1101100 x CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin OEx bit True O/P Comp. O/P 0X X X Low Low 1 Running 0 X Low Low 1 Running 1 0 Running Running 1 Running 1 1 Low Low Power Connections Pin Number Description VDD VDDIO GND Input receiver 58 analog 12 9 Digital power 20,30,31,38 13,21,31,39,47 22,29,40 DIF outputs Note: EPAD on this device is not electrically connected to the die. It should be connected to ground for best thermal performance. 9-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 2 MARCH 9, 2017 VDDIO CKPWRGD PD vOE0 VDDIO DIF0 vOE7 DIF0 DIF7 vOE1 DIF7 DIF1 vOE6 DIF1 DIF6 VDD1.5 DIF6 VDDIO GND GND VDDIO DIF2 VDD1.5 DIF2 vOE5