4-Output 1.8V PCIe Zero-Delay/Fanout 9DBV 0431 Clock Buffer with Zo = 33Ohms D ATA S HE E T Description Features/Benefits The 9DBV0431 is a member of Renesas SOC-Friendly 1.8V LP-HCSL outputs save 8 resistors minimal board space Very-Low-Power (VLP) PCIe family. It can also be used for and BOM cost 50M or 125M Ethernet Applications via software frequency 53mW typical power consumption in PLL mode minimal selection. The device has 4 output enables for clock power consumption management, and 3 selectable SMBus addresses. OE pins support DIF power management HCSL compatible differential input can be driven by Recommended Application common clock sources Programmable Slew rate for each output allows tuning for 1.8V PCIe Gen15 Zero-Delay/Fan-out Buffer (ZDB/FOB) various line lengths Programmable output amplitude allows tuning for various Output Features application environments Four 1200Hz Low-Power (LP) HCSL DIF pairs with Pin/software selectable PLL bandwidth and PLL Bypass ZO = 33ohms minimize phase jitter for each application Outputs blocked until PLL is locked clean system start-up Key Specifications Software selectable 50MHz or 125MHz PLL operation useful for Ethernet applications DIF cycle-to-cycle jitter < 50ps Configuration can be accomplished with strapping pins DIF output-to-output skew < 50ps SMBus interface not required for device control PCIe Gen5 CC additive phase jitter < 40fs RMS 3.3V tolerant SMBus interface works with legacy controllers 12kHz20MHz additive phase jitter = 156fs RMS at Space saving 5 x 5mm 32-VFQFPN minimal board space 156.25MHz (typical) Selectable SMBus addresses multiple devices can easily share an SMBus segment Block Diagram vOE(3:0) 4 CLK IN DIF3 SS- DIF2 Compatible PLL DIF1 vSADR DIF0 vHIBW BYPM LOBW CONTROL CKPWRGD PD LOGIC SDATA 3.3 SCLK 3.3 9DBV0431 R31DS0071EU0600 JULY 29, 2021 1 2021 Renesas Electronics Corporation C LK IN 9DBV0431 DATASHEET Pin Configuration 32 31 30 29 28 27 26 25 vHIBW BYPM LOBW 1 vOE2 24 FB DNC 2 DIF2 23 FB DNC 3 22 DIF2 9DBV0431 VDDR1.8 4 21 VDDA1.8 CLK IN 5 GNDA 20 epad is Gnd CLK IN 6 DIF1 19 GNDR 7 DIF1 18 GNDDIG 817vOE1 9 10111213141516 32-pin VFQFPN, 5x5 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table + Read/Write bit SADR Address x 0 1101011 State of SADR on first application of x M 1101100 CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin PLL OEx bit True O/P Comp. O/P 0 X X X Low Low Off 1 1 Running 0 X Low Low On 1 1 Running 1 0 Running Running On 1 1 Running 1 1 Low Low On 1. If Bypass mode is selected, the PLL will be off, and outputs will be running. Power Connections PLL Operating Mode Pin Number Byte1 7:6 Byte1 4:3 Description VDD GND HiBW BypM LoBW MODE Readback Control 47 Input receiver analog 0 PLL Lo BW 00 00 M Bypass 01 01 98 Digital Power 16, 25 15,20,26,30 DIF outputs 1 PLL Hi BW 11 11 21 20 PLL Analog Frequency Select Table FSEL CLK IN DIFx Byte3 4:3 (MHz) (MHz) 00 (Default) 100.00 CLK IN 01 50.00 CLK IN 10 125.00 CLK IN 11 Reserved Reserved 4-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 2 R31DS0071EU0600 JULY 29, 2021 VDDDIG1.8 SADR tri SCLK 3.3 CKPWRGD PD SDATA 3.3 GND vOE0 vOE3 DIF0 DIF3 DIF0 DIF3 GND GND VDDO1.8 VDDO1.8