9DBV0441AKLF Renesas

4-Output 1.8V PCIe Zero-Delay/Fanout 9DBV0441 Clock Buffer with Zo = 100ohms Datasheet Description Features/Benefits The 9DBV0441 is a member of Renesas SOC-Friendly Direct connection to 100 transmission lines saves 16 1.8V Very-Low-Power (VLP) PCIe family. It has integrated resistors compared to standard HCSL outputs output terminations providing Zo = 100 for direct 53mW typical power consumption in PLL mode minimal connection to 100 transmission lines. The device has 4 power consumption output enables for clock management, and 3 selectable Spread Spectrum (SS) compatible allows use of SS for SMBus addresses. EMI reduction OE pins support DIF power management Typical Applications HCSL compatible differential input can be driven by common clock sources 1.8V PCIe Gen15 Zero-Delay/Fan-out Buffer (ZDB/FOB) Programmable Slew rate for each output allows tuning for various line lengths Programmable output amplitude allows tuning for Output Features various application environments Four 1200MHz Low-Power (LP) HCSL DIF pairs with Pin/software selectable PLL bandwidth and PLL Bypass ZO = 100 minimize phase jitter for each application Outputs blocked until PLL is locked clean system Key Specifications start-up DIF cycle-to-cycle jitter < 50ps Software selectable 50MHz or 125MHz PLL operation useful for Ethernet applications DIF output-to-output skew < 50ps Configuration can be accomplished with strapping pins PCIe Gen5 CC additive phase jitter < 40fs RMS SMBus interface not required for device control 12kHz20MHz additive phase jitter = 156fs RMS at 3.3V tolerant SMBus interface works with legacy 156.25MHz (typical) controllers Space saving 5 5mm 32-VFQFPN minimal board space Selectable SMBus addresses multiple devices can easily share an SMBus segment Block Diagram vOE(3:0) DIF3 CLK IN DIF2 ZDB PLL CLK IN DIF1 SADR tri vHIBW BYPM LOBW DIF0 CONTROL CKPWRGD PD LOGIC SDATA 3.3 SCLK 3.3 2021 Renesas Electronics Corporation 1 R31DS0072EU0800 July 29, 20219DBV0441 Datasheet Pin Configuration 32 31 30 29 28 27 26 25 vHIBW BYPM LOBW 1 24 vOE2 FB DNC 2 23 DIF2 FB DNC 3 DIF2 22 VDDR1.8 4 VDDA1.8 21 9DBV0441 CLK IN 5 GNDA 20 CLK IN 6 19 DIF1 GNDR 7 18 DIF1 GNDDIG 817vOE1 9 10111213141516 32-pin VFQFPN, 5x5 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table + Read/Write bit SADR Address x 0 1101011 State of SADR on first application of x M 1101100 CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin PLL OEx bit True O/P Comp. O/P 0 X X X Low Low Off 1 1 Running 0 X Low Low On 1 1 Running 1 0 Running Running On 1 1 Running 1 1 Low Low On 1. If Bypass mode is selected, the PLL will be off, and outputs will be running. 2021 Renesas Electronics Corporation 2 R31DS0072EU0800 July 29, 2021 VDDDIG1.8 SADR tri SCLK 3.3 CKPWRGD PD SDATA 3.3 GND vOE0 vOE3 DIF0 DIF3 DIF0 DIF3 GND GND VDDO1.8 VDDO1.8