9DBV0831AKLF Renesas

8-Output 1.8V PCIe Zero-Delay/Fanout 9DBV 0831 Clock Buffer with Zo = 33Ohms D ATA S HE E T Description Features/Benefits The 9DBV0831 is a member of Renesas SOC-Friendly 1.8V LP-HCSL outputs save 16 resistors minimal board space Very-Low-Power (VLP) PCIe family. It can also be used for and BOM cost 50M or 125M Ethernet Applications via software frequency 62mW typical power consumption in PLL mode minimal selection. The device has 8 output enables for clock power consumption management, and 3 selectable SMBus addresses. Spread Spectrum (SS) compatible allows use of SS for EMI reduction Recommended Application OE pins support DIF power management HCSL compatible differential input can be driven by 1.8V PCIe Gen15 Zero Delay/Fanout Buffer (ZDB/FOB) common clock sources Programmable Slew rate for each output allows tuning for Output Features various line lengths Eight 1200Hz Low-Power (LP) HCSL DIF pairs with Programmable output amplitude allows tuning for various ZO = 33ohms application environments Pin/software selectable PLL bandwidth and PLL Bypass Key Specifications minimize phase jitter for each application Outputs blocked until PLL is locked clean system start-up DIF cycle-to-cycle jitter < 50ps Software selectable 50MHz or 125MHz PLL operation DIF output-to-output skew < 50ps useful for Ethernet applications PCIe Gen5 CC additive phase jitter < 40fs RMS Configuration can be accomplished with strapping pins 12kHz20MHz additive phase jitter = 156fs RMS at SMBus interface not required for device control 156.25M (typical) 3.3V tolerant SMBus interface works with legacy controllers Space saving 6 x 6mm 48-VFQFPN minimal board space Selectable SMBus addresses multiple devices can easily share an SMBus segment Block Diagram vOE(7:0) 8 DIF7 DIF6 CLK IN SS- DIF5 Compatible PLL DIF4 vSADR DIF3 vHIBW BYPM LOBW CONTROL DIF2 CKPWRGD PD LOGIC SDATA 3.3 DIF1 SCLK 3.3 DIF0 9DBV0831 R31DS0069EU0900 July 26, 2021 1 2021 Renesas Electronics Corporation CLK IN 9DBV0831 DATASHEET Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 vSADR tri 1 36 DIF5 vHIBW BYPM LOBW 2 35 DIF5 FB DNC 3 34 vOE4 FB DNC 4 33 DIF4 VDDR1.8 5 32 DIF4 9DBV0831 CLK IN 6 31 VDDIO EPAD should be CLK IN 7 30 VDDA1.8 GNDR 8 29 GNDA connected to GND GNDDIG 9 28 vOE3 SCLK 3.3 10 27 DIF3 SDATA 3.3 11 26 DIF3 VDDDIG1.812 25vOE2 13 14 15 16 17 18 19 20 21 22 23 24 48-pin VFQFPN, 6x6 mm, 0.4mm pitch AND pull v prefix indicates internal 120KOhm pull up down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor prefix indicates internal 120KOhm pull up resistor SMBus Address Selection Table SADR Address + Read/Write bit x 0 1101011 State of SADR on first application of x M 1101100 CKPWRGD PD x 1 1101101 Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin PLL OEx bit True O/P Comp. O/P 0X X X Low Low Off 1 1 Running 0 X Low Low On 1 1 Running 1 0 Running Running On 1 1 Running 1 1 Low Low On 1. If Bypass mode is selected, the PLL will be off, and outputs will be running. 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 2 R31DS0069EU0900 JULY 26, 2021 VDDIO CKPWRGD PD vOE0 VDDIO DIF0 vOE7 DIF0 DIF7 vOE1 DIF7 DIF1 vOE6 DIF1 DIF6 VDD1.8 DIF6 VDDIO GND GND VDDIO DIF2 VDD1.8 DIF2 vOE5