8-Output 1.8V PCIe Zero-Delay/Fanout 9DBV 0841 Clock Buffer with Zo = 100ohms D ATA S HE E T Description Features/Benefits The 9DBV0841 is a 1.8V member of Renesas full featured LP-HCSL outputs save 32 resistors minimal board space PCIe family. It has integrated output terminations providing and BOM cost Zo = 100 for direct connection for 100 transmission lines. 62mW typical power consumption in PLL mode eliminates The device has 8 output enables for clock management and 3 thermal concerns selectable SMBus addresses. Spread Spectrum (SS) compatible allows use of SS for EMI reduction Typical Applications OE pins support DIF power management HCSL compatible differential input can be driven by SSD, microServers, WLAN Access points common clock sources Programmable Slew rate for each output allows tuning for Output Features various line lengths Eight 1200MHz Low-Power (LP) HCSL DIF pairs Programmable output amplitude allows tuning for various application environments Key Specifications Pin/software selectable PLL bandwidth and PLL Bypass minimize phase jitter for each application DIF cycle-to-cycle jitter < 50ps Outputs blocked until PLL is locked clean system start-up DIF output-to-output skew < 50ps Software selectable 50MHz or 125MHz PLL operation PCIe Gen5 CC additive phase jitter < 40fs RMS useful for Ethernet applications 12kHz20MHz additive phase jitter = 156fs RMS at Configuration can be accomplished with strapping pins 156.25M (typical) SMBus interface not required for device control 3.3V tolerant SMBus interface works with legacy controllers Space saving 6 6 mm 48-VFQFPN minimal board space Selectable SMBus addresses multiple devices can easily share an SMBus segment Block Diagram vOE(7:0) 8 DIF7 DIF6 CLK IN SS DIF5 Compatible DIF4 PLL vSADR DIF3 vHIBW BYPM LOBW DIF2 Control CKPWRGD PD Logic DIF1 SDATA 3.3 SCLK 3.3 DIF0 9DBV0841 R31DS0070EU0700 JULY 27, 2021 1 2021 Renesas Electronics Corporation CLK IN 9DBV0841 DATASHEET Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 vSADR tri 1 36 DIF5 vHIBW BYPM LOBW 2 35 DIF5 FB DNC 3 34 vOE4 FB DNC 4 33 DIF4 VDDR1.8 5 32 DIF4 9DBV0841 CLK IN 6 31 VDDIO EPAD should be CLK IN 7 30 VDDA1.8 connected to GND GNDR 8 29 GNDA GNDDIG 9 28 vOE3 SCLK 3.3 10 27 DIF3 SDATA 3.3 11 26 DIF3 VDDDIG1.8 12 25 vOE2 13 14 15 16 17 18 19 20 21 22 23 24 48-pin VFQFPN, 6x6 mm, 0.4mm pitch v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor prefix indicates internal 120KOhm pull up resistor SMBus Address Selection Table + Read/Write bit SADR Address x 0 1101011 State of SADR on first application of x M 1101100 CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin PLL OEx bit True O/P Comp. O/P 0 X X X Low Low Off 1 1 Running 0 X Low Low On 1 1 Running 1 0 Running Running On 1 1 Running 1 1 Low Low On 1. If Bypass mode is selected, the PLL will be off, and outputs will be running. Power Connections Frequency Select Table FSEL CLK IN DIFx Pin Number Description Byte3 4:3 (MHz) (MHz) VDD VDDIO GND 00 (Default) 100.00 CLK IN Input 01 50.00 CLK IN 58 receiver 10 125.00 CLK IN analog 11 Reserved Reserved 12 9 Digital Power 13, 21, 31, 20, 31, 38 22, 29, 40 DIF outputs PLL Operating Mode 39, 47 Byte1 7:6 Byte1 4:3 30 29 PLL Analog HiBW BypM LoBW MODE Readback Control 0 PLL Lo BW 00 00 MBypass 01 01 1 PLL Hi BW 11 11 8-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 2 R31DS0070EU0700 JULY 27, 2021 VDDIO CKPWRGD PD vOE0 VDDIO DIF0 vOE7 DIF0 DIF7 vOE1 DIF7 DIF1 vOE6 DIF1 DIF6 VDD1.8 DIF6 VDDIO GND GND VDDIO DIF2 VDD1.8 DIF2 vOE5