2:4 3.3V PCIe Gen15 Clock Mux 9DML0441 / 9DML0451 DATASHEET Description Features The 9DML0441 and 9DML0451 devices are 3.3V members of Direct connection to 100 (xx41) or 85 (xx51) IDT s Full-Featured PCIe family. They support PCIe Gen15 transmission lines saves up to 16 resistors Common Clocked (CC), Separate Reference no Spread 79mW typical power consumption (SRnS), and Separate Reference Independent Spread Spread Spectrum Clocking (SSC) compatible (SRIS) architectures. The parts provide a choice of OE pins for each output asynchronous or glitch-free, gapped-clock switching modes, HCSL-compatible differential inputs and offer a choice of integrated output terminations for direct Selectable asynchronous or glitch-free, gapped-clock connection to 85 or 100 transmission lines. switching allows the mux to be selected at power up even if both inputs are not running, then transition to glitch-free Typical Applications switching mode Servers Space saving 4 4 mm 24-VFQFPN ATE Contact factory for customized versions Storage Master/Slave applications Key Specifications PCIe Gen15 CC support Output Features PCIe Gen15 SRIS support Four 1200MHz Low-Power HCSL (LP-HCSL) DIF pairs Output-to-output skew < 50ps 9DML0441 default ZOUT = 100 PCIe Gen5 additive jitter (CC) is < 0.06 ps rms 9DML0451 default ZOUT = 85 12kHz20MHz additive phase jitter 285fs rms typical See AN-891 for easy termination to other logic levels at156.25MHz Block Diagram VDDR3.3 x2 VDD3.3 4 OE(3:0) DIF3 DIF INA DIF3 A DIF INA DIF2 DIF2 DIF INB B DIF1 DIF INB DIF1 vSW MODE DIF0 SEL A B DIF0 EPAD/GND GNDR x2 GND Note: Default resistors are internal on 41/51 devices. 9DML0441 / 9DML0451 MAY 22, 2019 19DML0441 / 9DML0451 DATASHEET Pin Configuration 24 23 22 21 20 19 DIF INA 1 DIF2 18 9DML0441 DIF INA 2 17 DIF2 9DML0451 VDDR3.3 3 VDD3.3 16 VDDR3.3 4 Connect EPAD to GND 15 5 DIF1 GND DIF INB 14 DIF INB 6 DIF1 13 7 8 9 101112 24-VFQFPN, 4 x 4 mm, 0.5mm pitch prefix indicates internal pull-up resistor v prefix indicates internal pull-down resistor Power Management Table DIFx OEx Pin DIF IN True O/P Comp. O/P 0 Running Running Running 1 Running Low Low Power Connections Pin Number Description VDD GND 324 Input A receiver analog 47 Input B receiver analog 16 15 DIF outputs 2:4 3.3V PCIE GEN15 CLOCK MUX 2 MAY 22, 2019 GNDR GNDR vSW MODE SEL A B OE0 OE3 DIF0 DIF3 DIF0 DIF3 OE1 OE2