4:4 Clock MUX for PCI Express 9DML4493A Gen15 Datasheet Description Features Four differential inputs support LVPECL, LVDS, HCSL or The 9DML4493A is a 4-input, 4-output clock multiplexer. It can LVCMOS reference clocks also operate as a dual 2-input, 2-output clock multiplexer. It has very low additive phase jitter and is suitable for all PCIe data Flexible Power Sequencing (FPS) ensures good behavior rates. Pin straps configure the device, making it ideal for when powered up without input clock, or when the input clock applications where a serial configuration bus is not available. is present without power Power-Down Tolerant (PDT) inputs: CLK SEL tri, OE pins, The device supports today s complex system power sequencing IOA tri, IOB tri, ZOUTSEL may be driven when the 9DML4493 requirements with Power Down Tolerant and Flexible Power is not powered up Sequencing features. Accepts input frequencies ranging from 1PPS (1Hz) to 350MHz Strapping pin selects differential output impedances of 100 or Typical Applications 85, saving up to 16 resistors Servers Three pin-selectable output amplitudes per bank Storage Pin selectable 4:4 mode or dual 2:2 MUX mode Networking Glitch-free output enable pins for each output High-Performance computing Spread spectrum tolerant Accelerators Voltage supply of 1.8V, 2.5V, or 3.3V -40C to +85C ambient operating temperature Key Specifications 5 5 mm 32-VFQFPN package Additive phase jitter: 12fs RMS typical (PCIe Gen5 CC at 100MHz) 66fs RMS typical (12kHz20MHz at 156.25M) Supports PCIe Gen15 PCIe Refclk requirements Supports PCIe CC and IR (SRIS, SRNS) timing architectures Propagation delay < 1.2ns typical Block Diagram VDDCLK x4 VDDCORE VDDOA VDDOB 2 vOEA 1:0 2 vCLK SEL tri 1:0 CLKA0 CLKIN0 CLKA0 CLKIN0 CLKA1 CLKIN3 CLKA1 CLKIN3 CLKIN1 CLKB0 CLKIN1 CLKB0 CLKIN2 CLKB1 CLKIN2 CLKB1 2 vOEB 1:0 vIOA tri vIOB tri Logic ZOUTSEL EPAD is GND 2021 Renesas Electronics Corporation 1 February 19, 20219DML4493A Datasheet Contents Description 1 Typical Applications . 1 Key Specifications 1 Features 1 Block Diagram . 1 Pin Assignments 3 Clock Input Bias Network 3 Pin Descriptions 4 Absolute Maximum Ratings . 6 Electrical Characteristics . 7 Test Loads . 19 Alternate Terminations 19 Phase Jitter Test Loads . 20 Package Outline Drawings . 21 Thermal Characteristics . 21 Marking Diagram 21 Ordering Information . 21 Revision History . 22 2021 Renesas Electronics Corporation 2 February 19, 2021