DATASHEET 15 Output PCIe G2/QPI Differential Buffer with 9EX21501A 2:1 Input Mux Description Features/Benefits: The ICS9EX21501 provides 15 output clocks for PCIe Gen2 Output clock frequencies up to 400 MHz/supports wide (100MHz) or QPI (133MHz) applications. A differential CPU clock range of applications from a CK410B+ main clock generator, such as the ICS932S421, 4 Selectable SMBus addresses/multiple devices can share drives the ICS9EX21501. In fanout mode, the ICS9EX21501 SMBus segment provides outputs up to 400MHz. A 2:1 input mux allows selection SMBus address independent of PLL operating mode/ between local and remote clock sources. maximum flexibility Recommended Application: Dedicated CKPWRGD/PD and VDDA pins/Easy board design 15 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 8 Dedicated OE and 2 Group OE pins/Support for hardware clock management Key Specifications: DIF output cycle-to-cycle jitter < 50ps Output Features: DIF output-to-output skew < 150 ps 15 - 0.7V current-mode differential HCSL output pairs PCIe Gen2 compliant phase jitter Supports zero delay buffer mode and fanout mode QPI 6.4Gb/s 12UI compliant phase jitter Selectable PLL bandwidth 80-150 MHz in PLL Mode 33-400 MHz operation in Bypass mode Functional Block Diagram OE13 14 10 OE(5:12) , OE 01234 CLKA IN PLL CLKA IN (SS Compatible) 15 DIF(14:0) CLKB IN CLKB IN HIBW BYPM LOBW 100M 133M CKPWRGD/PD SMB A0 Logic SMB A1 SEL A B SMBDAT SMBCLK IREF IDT 15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux 157807/18/11 1DIF 0 DIF 0 OE 01234 VDD CLKB IN CLKB IN GND CLKA IN CLKA IN VDDA GNDA IREF DIF 14 DIF 14 OE13 14 VDD 9EX21501 Datasheet 15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux PIn Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 OE9 1 48 DIF 6 DIF 9 2 47 DIF 6 DIF 9 3 46 OE6 OE10 4 45 DIF 5 DIF 10 5 44 DIF 5 DIF 10 6 43 OE5 OE11 7 42 DIF 4 DIF 11 8 41 DIF 4 9EX21501 DIF 11 9 40 DIF 3 GND 10 39 DIF 3 VDD 11 38 GND DIF 12 12 37 VDD DIF 12 13 36 DIF 2 OE12 14 35 DIF 2 DIF 13 15 34 DIF 1 DIF 13 16 33 DIF 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64-pin MLF Power Groups Frequency/Functionality Table Pin Number Byte 0, Description bit 2 Byte 0, Byte 0, Input DIF x VDD GND (100 133M bit 1 bit 0 MHz MHz 23 22 Main PLL, Analog Latch) FSB FSA Notes 29 26 Input buffers 1 100.00 100.00 1 01 11,17,37,49, 64 10, 38 DIF clocks 0 01 133.33 133.33 1 01 1 166.67 166.67 2 Power Down Functionality 01 0 200.00 200.00 2 INPUTS OUTPUTS PLL State 00 0 266.67 266.67 2 CKPWRGD/PD Input DIF x 10 0 333.33 333.33 2 1 Running Running ON 11 0 400.00 400.00 2 0X Hi-Z OFF 11 1 Reserved SMBus Address Selection (pins 57, 58) Notes:100M 133M SMB A1 SMB A0 Address 1. Latch selects between 100 and 133 MHz. This is equivalent to FSC in CK410B+/CK509B FS table. 00 D4 2. Writing Byte 2 bits (2:0) can select other frequencies. 01 D6 These frequencies are not characterized in PLL Mode 10 D8 11 DA HIBW BYPM LOBW Selection (Pin 54) State Voltage Mode Low <0.8V Low BW Mid 1.2<Vin<1.8V Bypass High Vin > 2.0V High BW IDT 15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux 157801/18/11 2 VDD OE8 DIF 8 DIF 8 CKPWRGD/PD SEL A B SMB A0 SMB A1 SMBDAT SMBCLK HIBW BYPM LOBW 100M 133M DIF 7 DIF 7 OE7 VDD