DATASHEET Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 ICS9FG1200D-1 & FBD Description Features/Benefits ICS9FG1200D-1 follows the Intel DB1200GS Differential Buffer Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs) Specification. This buffer provides 12 output clocks for CPU Host Power up default is all outputs in 1:1 mode Bus, PCIe Gen2, or Fully Buffered DIMM applications. The outputs DIF (9:0) can be gear-shifted from the input CPU Host are configured with two groups. Both groups (DIF 9:0) and (DIF Clock 11:10) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410B+ main clock generator, DIF (11:10) can be gear-shifted from the input CPU such as the ICS932S421, drives the . The Host Clock can provide outputs up to 400MHz. Spread spectrum compatible Supports output clock frequencies up to 400 MHz 8 Selectable SMBus addresses SMBus address determines PLL or Bypass mode Key Specifications DIF output cycle-to-cycle jitter < 50ps DIF output-to-output skew < 100ps across all outputs in 1:1 mode 56-pin SSOP/TSSOP package RoHS compliant packaging Functional Block Diagram OE SPREAD 2 STOP COMPATIBLE DIF(11:10) LOGIC 1:1 PLL 10 OE(9:0) CLK IN SPREAD 10 STOP COMPATIBLE DIF(9:0) LOGIC GEARING PLL CLK IN HIGH BW FS A 410 VTT PWRGD /PD CONTROL SMB A0 SMB A1 LOGIC SMB A2 PLLBYP SMBDAT SMBCLK IREF IDT Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 02/08/10 1ICS9FG1200D-1 Pin Configuration HIGH BW 1 56 VDDA CLK IN 2 55 GNDA CLK IN 3 54 IREF SMB A0 4 53 OE10 11 OE0 5 52 DIF 11 DIF 0 6 51 DIF 11 DIF 0 7 50 VDD OE1 8 49 GND DIF 1 9 48 DIF 10 DIF 1 10 47 DIF 10 VDD 11 46 FS A 410 GND 12 45 VTT PWRGD /PD DIF 2 13 44 OE9 DIF 2 14 43 DIF 9 OE2 15 42 DIF 9 DIF 3 16 41 OE8 DIF 3 17 40 DIF 8 OE3 18 39 DIF 8 DIF 4 19 38 VDD DIF 4 20 37 GND OE4 21 36 DIF 7 VDD 22 35 DIF 7 GND 23 34 OE7 DIF 5 24 33 DIF 6 DIF 5 25 32 DIF 6 OE5 26 31 OE6 SMB A1 27 30 SMB A2 PLLBYP SMBDAT 28 29 SMBCLK 56-pin SSOP & TSSOP Power Groups Pin Number Description VDD GND 56 55 Main PLL, Analog 11,22,38,50 12,23,37,49 DIF clocks Functionality at Power Up (PLL Mode) CLK IN (CPU FSB) DIF (11:0) 1 FS A 410 MHz MHz 1 100 <= CLK IN < 200 CLK IN 0 200<= CLK IN <= 400 CLK IN 1. FS A 410 is a low-threshold input. Please see the V and V IL FS IH FS specifications in the Input/Supply/Common Output Parameters Table for correct values. IDT Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 02/08/10 2 9FG1200-1