DATASHEET ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Description Features/Benefits The ICS9FG1201H follows the Intel DB1200G Rev 1.0 Differential Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs) Buffer Specification. This buffer provides 12 output clocks for CPU Power up default is all outputs in 1:1 mode Host Bus, PCI-Express, or Fully Buffered DIMM applications. The DIF (9:0) can be gear-shifted from the input CPU Host outputs are configured with two groups. Both groups (DIF 9:0) and Clock (DIF 11:10) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410B or CK410B+ main clock DIF (11:10) can be gear-shifted from the input CPU Host generator, such as the ICS932S421, drives the ICS9FG1201. The Clock ICS9FG1201H can provide outputs up to 400MHz Spread spectrum compatible Supports output clock frequencies up to 400 MHz 8 Selectable SMBus addresses SMBus address determines PLL or Bypass mode Key Specifications DIF output cycle-to-cycle jitter < 50ps DIF output-to-output skew < 50ps within a group DIF output-to-output skew < 100ps across all outputs 56-pin SSOP/TSSOP package RoHS compliant packaging Functional Block Diagram OE SPREAD GEAR 2 STOP COMPATIBLE SHIFT DIF(11:10) LOGIC PLL LOGIC 10 OE(9:0) SPREAD GEAR CLK IN 10 STOP COMPATIBLE SHIFT DIF(9:0) LOGIC CLK IN PLL LOGIC HIGH BW FS A 410 VTT PWRGD /PD SMB A0 CONTROL SMB A1 LOGIC SMB A2 PLLBYP SMBDAT SMBCLK IREF TM TM IDT /ICS Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD 1371F 09/23/09 1ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Pin Configuration HIGH BW 1 56 VDDA CLK IN 2 55 GNDA CLK IN 3 54 IREF SMB A0 4 53 OE10 11 OE0 5 52 DIF 11 DIF 0 6 51 DIF 11 DIF 0 7 50 VDD OE1 8 49 GND DIF 1 9 48 DIF 10 DIF 1 10 47 DIF 10 VDD 11 46 FS A 410 GND 12 45 VTT PWRGD /PD DIF 2 13 44 OE9 DIF 2 14 43 DIF 9 OE2 15 42 DIF 9 DIF 3 16 41 OE8 DIF 3 17 40 DIF 8 OE3 18 39 DIF 8 DIF 4 19 38 VDD DIF 4 20 37 GND OE4 21 36 DIF 7 VDD 22 35 DIF 7 GND 23 34 OE7 DIF 5 24 33 DIF 6 DIF 5 25 32 DIF 6 OE5 26 31 OE6 SMB A1 27 30 SMB A2 PLLBYP SMBDAT 28 29 SMBCLK 56-pin SSOP & TSSOP Functionality Table CLK IN (CPU FSB) DIF (9:0) Output DIF (11:10) Output 1 FS A 410 MHz MHz MHz 1 100.00 100.00 100.00 1 133.33 133.33 133.33 1 166.66 166.66 166.66 1 RESERVED 0 200.00 200.00 200.00 0 266.66 266.66 266.66 0 333.33 333.33 333.33 0 400.00 400.00 400.00 1. FS A 410 is a low-threshold input. Please see the V and V IL FS IH FS specifications in the Input/Supply/Common Output Parameters Table for correct values. TM TM IDT /ICS Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD 1371F 09/23/09 2 ICS9FG1201H