SMB A1 SMB A0 DIF 8 DIF 8 OE8 DIF 7 DIF 7 OE7 GND VDD DIF 6 DIF 6 OE6 DIF 5 DIF 5 OE5 SMBDAT SMBCLK Integrated ICS9FG1901 Circuit Systems, Inc. Frequency Generator for P4 CPU, PCI Express & Fully Buffered DIMM Clocks Functionality at Power Up (PLL Mode) Recommended Application: CLK IN (CPU FSB) DIF (18:0) DB1900G: CPU Host Bus, PCI Express and Fully-Buffered 1 FS A 410 DIMM clocking MHz MHz 1 100 <= CLK IN < 200 CLK IN Features: 0 200<= CLK IN <= 400 CLK IN Power up default is all outputs in 1:1 mode 1. FS A 410 is a low-threshold input. Please see the V and V IL FS IH FS DIF (16:0) can be gear-shifted from the input CPU specifications in the Input/Supply/Common Output Parameters Table for Host Clock correct values. DIF (18:17) can be gear-shifted from the input CPU Host Clock Spread spectrum compatible Power Down Functionality Supports output clock frequencies up to 400 MHz INPUTS OUTPUTS PLL State 8 Selectable SMBus addresses VDDA/PD CLK IN/CLK IN DIF DIF 3.3V (NOM) Running Running ON SMBus address determines PLL or Bypass mode Hi-Z GND X OFF VDDA controlled power down mode Functionality Note It is recommended that Byte 2, bit 6 be toggled from 1 to 0 Key Specifications: and back to 1, the first time VDDA is applied. This ensures DIF output cycle-to-cycle jitter < 50ps proper initialization of the device. DIF (0:18) output-to-output skew < 225ps DIF (0:16) output-to-output skew < 100ps Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 IREF 1 54 OE14 GNDA 2 53 DIF 13 VDDA/PD 3 52 DIF 13 HIGH BW 4 51 OE13 FS A 410 5 50 DIF 12 DIF 0 6 49 DIF 12 DIF 0 7 48 OE12 DIF 1 8 47 VDD DIF 1 9 46 GND ICS9FG1901 GND 10 45 DIF 11 VDD 11 44 DIF 11 DIF 2 12 43 OE11 DIF 2 13 42 DIF 10 DIF 3 14 41 DIF 10 DIF 3 15 40 OE10 DIF 4 16 39 DIF 9 DIF 4 17 38 DIF 9 OE 01234 18 37 OE9 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72-pin MLF 0962E01/02/07 Other names and brands may be claimed as the property of others. SMB A2 PLLBYP CLK IN CLK IN OE17 18 DIF 18 DIF 18 DIF 17 DIF 17 GND VDD DIF 16 DIF 16 OE16 DIF 15 DIF 15 OE15 DIF 14 DIF 14Integrated ICS9FG1901 Circuit Systems, Inc. Pin Description PIN PIN NAME PIN TYPE DESCRIPTION This pin establishes the reference current for the differential current-mode output 1 IREF OUT pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 2 GNDA PWR Ground pin for the PLL core. 3.3V power for the PLL core that also functions as Power Down. Collapsing this 3 VDDA/PD PWR power supply places the device in Power Down mode. 3.3V input for selecting PLL Band Width 4HIGH BW IN 0 = High, 1= Low 3.3V tolerant low threshold input for CPU frequency selection. This pin requires 5FS A 410 IN CK410 FSA. Refer to input electrical characteristics for Vil FS and Vih FS threshold values. 6 DIF 0 OUT 0.7V differential true clock output 7 DIF 0 OUT 0.7V differential complement clock output 8 DIF 1 OUT 0.7V differential true clock output 9 DIF 1 OUT 0.7V differential complement clock output 10 GND PWR Ground pin. 11 VDD PWR Power supply, nominal 3.3V 12 DIF 2 OUT 0.7V differential true clock output 13 DIF 2 OUT 0.7V differential complement clock output 14 DIF 3 OUT 0.7V differential true clock output 15 DIF 3 OUT 0.7V differential complement clock output 16 DIF 4 OUT 0.7V differential true clock output 17 DIF 4 OUT 0.7V differential complement clock output Active low input for enabling DIF pairs 0, 1, 2, 3 and 4. 18 OE 01234 IN 1 = tri-state outputs, 0 = enable outputs 19 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant 20 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant Active low input for enabling DIF pair 5. 21 OE5 IN 1 = tri-state outputs, 0 = enable outputs 22 DIF 5 OUT 0.7V differential true clock output 23 DIF 5 OUT 0.7V differential complement clock output Active low input for enabling DIF pair 6. 24 OE6 IN 1 = tri-state outputs, 0 = enable outputs 25 DIF 6 OUT 0.7V differential true clock output 26 DIF 6 OUT 0.7V differential complement clock output 27 VDD PWR Power supply, nominal 3.3V 28 GND PWR Ground pin. Active low input for enabling DIF pair 7. 29 OE7 IN 1 = tri-state outputs, 0 = enable outputs 30 DIF 7 OUT 0.7V differential true clock output 31 DIF 7 OUT 0.7V differential complement clock output Active low input for enabling DIF pair 8. 32 OE8 IN 1 = tri-state outputs, 0 = enable outputs 33 DIF 8 OUT 0.7V differential true clock output 34 DIF 8 OUT 0.7V differential complement clock output 35 SMB A0 IN SMBus address bit 0 (LSB) 36 SMB A1 IN SMBus address bit 1 0962E01/02/07 2