SMB A1 SMB A0 DIF 8 DIF 8 OE8 DIF 7 DIF 7 OE7 GND VDD DIF 6 DIF 6 OE6 DIF 5 DIF 5 OE5 SMBDAT SMBCLK Integrated ICS9FG1904B-1 Circuit Systems, Inc. Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD Recommended Application: Functionality at Power Up (PLL Mode) DB1900GS/GSO with 15:4 output grouping CLK IN (CPU FSB) DIF (18:0) 1 FS A 410 MHz MHz Features: 1 100 <= CLK IN < 200 CLK IN Power up default is all outputs in 1:1 mode 0 200<= CLK IN <= 400 CLK IN DIF (14:0) can be gear-shifted from the input CPU FS A 410 is a low-threshold input. Please see the V and V 1. IL FS IH FS Host Clock specifications in the Input/Supply/Common Output Parameters Table for DIF (18:15) can be gear-shifted from the input CPU correct values. Host Clock Spread spectrum compatible Power Down Functionality Supports output clock frequencies up to 400 MHz INPUTS OUTPUTS 8 Selectable SMBus addresses CKPWRGD/ CLK IN/ PLL State SMBus address determines PLL or Bypass mode PD CLK IN DIF/DIF 1 Running Running ON 0X Hi-Z OFF Key Specifications: DIF output cycle-to-cycle jitter < 50ps DIF output-to-output skew < 100ps within a group Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 IREF 1 54 OE14 GNDA 2 53 DIF 13 VDDA 3 52DIF 13 HIGH BW 4 51 OE13 FS A 410 5 50 DIF 12 DIF 0 6 49 DIF 12 DIF 0 7 48 OE12 DIF 1 8 47 VDD DIF 1 9 46 GND ICS9FG1904-1 GND 10 45 DIF 11 VDD 11 44 DIF 11 DIF 2 12 43 OE11 DIF 2 13 42 DIF 10 DIF 3 14 41 DIF 10 DIF 3 15 40 OE10 DIF 4 16 39 DIF 9 DIF 4 17 38 DIF 9 OE 01234 18 37 OE9 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72-pin MLF 1255B08/03/07 Other names and brands may be claimed as the property of others. SMB A2 PLLBYP CLK IN CLK IN OE 17 18 DIF 18 DIF 18 DIF 17 DIF 17 GND VDD DIF 16 DIF 16 OE 15 16 DIF 15 DIF 15 CKPWRGD/PD DIF 14 DIF 14Integrated ICS9FG1904B-1 Circuit Systems, Inc. Pin Description PIN PIN NAME PIN TYPE DESCRIPTION This pin establishes the reference current for the differential current-mode 1 IREF OUT output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 2 GNDA PWR Ground pin for the PLL core. 3 VDDA PWR 3.3V power for the PLL core. 3.3V input for selecting PLL Band Width 4HIGH BW IN 0 = High, 1= Low 3.3V tolerant low threshold input for CPU frequency selection. This pin 5 FS A 410 IN requires CK410 FSA. Refer to input electrical characteristics for Vil FS and Vih FS threshold values. 6 DIF 0 OUT 0.7V differential true clock output 7 DIF 0 OUT 0.7V differential complement clock output 8 DIF 1 OUT 0.7V differential true clock output 9 DIF 1 OUT 0.7V differential complement clock output 10 GND PWR Ground pin. 11 VDD PWR Power supply, nominal 3.3V 12 DIF 2 OUT 0.7V differential true clock output 13 DIF 2 OUT 0.7V differential complement clock output 14 DIF 3 OUT 0.7V differential true clock output 15 DIF 3 OUT 0.7V differential complement clock output 16 DIF 4 OUT 0.7V differential true clock output 17 DIF 4 OUT 0.7V differential complement clock output Active low input for enabling DIF pairs 0, 1, 2, 3 and 4. 18 OE 01234 IN 1 = tri-state outputs, 0 = enable outputs 19 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant 20 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant Active low input for enabling DIF pair 5. 21 OE5 IN 1 = tri-state outputs, 0 = enable outputs 22 DIF 5 OUT 0.7V differential true clock output 23 DIF 5 OUT 0.7V differential complement clock output Active low input for enabling DIF pair 6. 24 OE6 IN 1 = tri-state outputs, 0 = enable outputs 25 DIF 6 OUT 0.7V differential true clock output 26 DIF 6 OUT 0.7V differential complement clock output 27 VDD PWR Power supply, nominal 3.3V 28 GND PWR Ground pin. Active low input for enabling DIF pair 7. 29 OE7 IN 1 = tri-state outputs, 0 = enable outputs 30 DIF 7 OUT 0.7V differential true clock output 31 DIF 7 OUT 0.7V differential complement clock output Active low input for enabling DIF pair 8. 32 OE8 IN 1 = tri-state outputs, 0 = enable outputs 33 DIF 8 OUT 0.7V differential true clock output 34 DIF 8 OUT 0.7V differential complement clock output 35 SMB A0 IN SMBus address bit 0 (LSB) 36 SMB A1 IN SMBus address bit 1 1255B08/03/07 2