DATASHEET ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Description Pin Configuration DDR I/DDR II Zero Delay Clock Buffer DDRC0 1 28 GND DDRT0 2 27 DDRC5 Output Features VDD2.5/1.8 3 26 DDRT5 Low skew, low jitter PLL clock driver DDRT1 4 25 VDD2.5/1.8 Max frequency supported = 400MHz (DDRII 800) DDRC1 5 24 GND 2 I C for functional and output control GND 6 23 DDRC4 Feedback pins for input to output synchronization VDDA2.5/1.8 7 22 DDRT4 Spread Spectrum tolerant inputs Programmable skew through SMBus GND 8 21 VDD2.5/1.8 Frequency defect control thorugh SMBus CLK INT 9 20 SDATA Individual output control programmable through SMBus CLK INC 10 19 SCLK VDD2.5/1.8 11 18 FB IN Key Specifications DDRT2 12 17 FB OUT CYCLE - CYCLE jitter: <100ps DDRC2 13 16 DDRT3 OUTPUT - OUTPUT skew: <100ps GND 14 15 DDRC3 DUTY CYCLE: 48% - 52% 28-SSOP/TSSOP 28-pin SSOP package Available in RoHS compliant packaging Operates 2.5V or 1.8V Funtional Block Diagram FB OUT Control SCLK DDRT0 DDRC0 SDATA Logic DDRT1 DDRC1 DDRT2 DDRC2 DDRT3 FB IN DDRC3 CLK INT PLL DDRT4 DDRC4 CLK INC DDRT5 DDRC5 TM TM IDT /ICS DDR I/DDR II Phase Lock Loop Zero Delay Buffer ICS9P935 REV H 12/1/08 1 ICS9P935ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Pin Description Pin Pin Name Type Pin Description 1 DDRC0 OUTComplementar Clock of differential pair output. 2 DDRT0 OUTTru Clock of differential pair output. 3 VDD2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V 4 DDRT1 OUTTru Clock of differential pair output. 5 DDRC1 OUTComplementar Clock of differential pair output. 6 GND PWR Ground pin. 7 VDDA2.5/1.8 PWR Output power supply, nominal 2.5V or 1.8V 8 GND PWR Ground pin. 9 CLK INT INTru reference clock input. 10 CLK INC INComplementar reference clock input. 11 VDD2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V 12 DDRT2 OUTTru Clock of differential pair output. 13 DDRC2 OUTComplementar Clock of differential pair output. 14 GND PWR Ground pin. 15 DDRC3 OUTComplementar Clock of differential pair output. 16 DDRT3 OUTTru Clock of differential pair output. 17 FB OUT OUT Feedback output, dedicated for external feedback. Single-ended feedback input, provides feedback signal to internal PLL to eliminate 18 FB IN IN phase error with the input clock. 19 SCLK IN Clock pin of SMBus circuitry, 3.3V tolerant. 20 SDATA I/O Data pin for SMBus circuitry, 3.3V tolerant. 21 VDD2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V 22 DDRT4 OUTTru Clock of differential pair output. 23 DDRC4 OUTComplementar Clock of differential pair output. 24 GND PWR Ground pin. 25 VDD2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V 26 DDRT5 OUTTru Clock of differential pair output. 27 DDRC5 OUTComplementar Clock of differential pair output. 28 GND PWR Ground pin. TM TM IDT /ICS DDR I/DDR II Phase Lock Loop Zero Delay Buffer ICS9P935 REV H 12/1/08 2