DATASHEET DUAL CHANNEL DDRII/III ZERO DELAY BUFFER 9P960 Recommended Application Pin Configuration Dual DDR zero delay buffer DDRAT0 1 48 FB OUTA DDRAC0 2 47 FB INTA DDRAT1 3 46 VDD1.8/1.5 Features/Benefits CLK INTA T DDRAC1 4 45 High performance, low jitter zero delay buffer DDRAT2 5 44 CLK INTA C 2 DDRAC2 6 43 GND I C for functional and output control GND 7 42 DDRAT3 Dual bank 1-6 differential clock distribution VDD1.8/1.5 8 41 DDRAC3 2 separate feedback in & out for input to output DDRAT4 AGND 9 40 synchronization for each bank AVDD1.8 10 39 DDRAC4 Supports up to 4 DDR DIMMs SCLK 11 38 DDRAT5 Supports up to DDRII - 1066MHz SDATA 12 37 DDRAC5 Supports up to DDRIII (1.8V core) - 1333MHz VDD1.8/1.5 VDD1.8/1.5 13 36 Output-to-output skew: <100ps DDRBT0 14 35 GND DDRBC0 15 34 AVDD1.8 DDRBT1 16 33 AGND DDRBC1 17 32 GND DDRBT2 18 31 VDD1.8/1.5 DDRBC2 19 30 DDRBT5 CLK INTB T 20 29 DDRBC5 CLK INTB C 21 28 DDRBT4 GND 22 27 DDRBC4 FB INTB 23 26 DDRBT3 FB OUTB 24 25 DDRBC3 48-SSOP Block Diagram IDT DUAL CHANNEL DDRII/III ZERO DELAY BUFFER 1 9P960 REV A 051811 ICS9P9609P960 DUAL CHANNEL DDRII/III ZERO DELAY BUFFER Pin Descriptions Pin Pin Name Type Pin Description 1 DDRAT0 OUTTru Clock of differential pair output. 2 DDRAC0 OUTComplementar Clock of differential pair output. 3DDRAT1 OUTTru Clock of differential pair output. 4DDRAC1 OUTComplementar Clock of differential pair output. 5 DDRAT2 OUTTru Clock of differential pair output. 6DDRAC2 OUTComplementar Clock of differential pair output. 7 GND PWR Ground pin. 8 VDD1.8/1.5 PWR Power supply, nominal 1.8V or 1.5V 9 AGND PWR Analog Ground pin for Core PLL 10 AVDD1.8 PWR 1.8V Analog Power pin for Core PLL 11 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 12 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. 13 VDD1.8/1.5 PWR Power supply, nominal 1.8V or 1.5V 14 DDRBT0 OUTTru Clock of differential pair output. 15 DDRBC0 OUTComplementar Clock of differential pair output. 16 DDRBT1 OUTTru Clock of differential pair output. 17 DDRBC1 OUTComplementar Clock of differential pair output. 18 DDRBT2 OUTTru Clock of differential pair output. 19 DDRBC2 OUTComplementar Clock of differential pair output. 20 CLK INTB T IN True reference clock input for ban k B. 21 CLK INTB C IN Complementary reference clock i nput for bank B. 22 GND PWR Ground pin. True single-ended feedback input, provides feedback signal to internal PLL for 23 FB INTB IN synchronization with CLK INTB to el iminate phase error on bank B. 24 FB OUTB OUT Feedback output, dedicated external feedback for bank B outputs. 25 DDRBC3 OUTComplementar Clock of differential pair output. 26 DDRBT3 OUTTru Clock of differential pair output. 27 DDRBC4 OUTComplementar Clock of differential pair output. 28 DDRBT4 OUTTru Clock of differential pair output. 29 DDRBC5 OUTComplementar Clock of differential pair output. 30 DDRBT5 OUTTru Clock of differential pair output. 31 VDD1.8/1.5 PWR Power supply, nominal 1.8V or 1.5V 32 GND PWR Ground pin. 33 AGND PWR Analog Ground pin for Core PLL 34 AVDD1.8 PWR 1.8V Analog Power pin for Core PLL 35 GND PWR Ground pin. 36 VDD1.8/1.5 PWR Power supply, nominal 1.8V or 1.5V 37 DDRAC5 OUTComplementar Clock of differential pair output. 38 DDRAT5 OUTTru Clock of differential pair output. 39 DDRAC4 OUTComplementar Clock of differential pair output. 40 DDRAT4 OUTTru Clock of differential pair output. 41 DDRAC3 OUTComplementar Clock of differential pair output. 42 DDRAT3 OUTTru Clock of differential pair output. 43 GND PWR Ground pin. 44 CLK INTA C IN Complementary reference clock i nput for bank A. 45 CLK INTA T IN True reference clock input for ban k A. 46 VDD1.8/1.5 PWR Power supply, nominal 1.8V or 1.5V True single-ended feedback input, provides feedback signal to internal PLL for 47 FB INTA IN synchronization with CLK INTA to el imate phase error on bank A. 48 FB OUTA OUT Feedback output, dedicated external feedback for bank A outputs. IDT DUAL CHANNEL DDRII/III ZERO DELAY BUFFER 2 9P960 REV A 051811