2-output CK420BQ Derivative 9SQL4952 DATASHEET Description Features/Benefits The 9SQL4952 is a member of IDT s Lite family of server Direct connection to 85 transmission lines saves 8 2 clocks. It generates 2 100MHz outputs that exceed the resistors and 14mm compared to standard HCSL requirements of the CK420BQ CPU/SRC clocks. Each output 112mW typical power consumption eases thermal has its own OE pin for clock management and supports 2 concerns 1/10 the power of CK420BQ different spread spectrum levels in addition to spread off. It Contains default configuration SMBus interface not also provides a copy of the 25MHz internal XO. The required for device operation 9SQL4952 supports PCIe Common Clock (CC) and OE pins support BCLK power management Independent Reference Clock (IR) architectures. 25MHz input frequency standard crystal Recommended Application 25MHz REF output eliminates XO from board Pin/SMBus selectable 0%, -0.25% or -0.5% spread on PCIe Gen1, Gen2, Gen3, Gen4 Server Clock BCLK outputs minimize EMI and phase jitter for each Output Features application BCLK outputs blocked until PLL is locked clean system 2-100MHz push-pull Low-power (LP) HCSL BCLK pairs start-up Integrated terminations for 85 Zout Two selectable SMBus addresses multiple devices can 1 - 3.3V 25MHz LVCMOS REF output easily share an SMBus segment Key Specifications Space saving 24-pin 4x4mm VFQFPN minimal board space BCLK outputs: Cycle-to-cycle jitter <50ps Output-to-output skew <50ps PCIe Gen1, Gen2, Gen3, Gen4 CC compliant PCIe Gen2, Gen3 IR compliant QPI/UPI compliant SAS12G compliant (SSC off) 12k-20M phase jitter <2ps rms (SSC off) REF output: Phase jitter <200fs rms (SSC off) 50ppm frequency accuracy on all clocks Block Diagram p REF vOE(1:0) 2 XIN/CLKIN 25 X2 SSC BCLK1 Capable BCLK0 PLL vSADR vSS EN tri CKPWRGD PD Control Logic SDATA 3.3 SCLK 3.3 9SQL4952 DECEMBER 12, 2016 1 2016 Integrated Device Technology, Inc.9SQL4952 DATASHEET Pin Configuration 24 23 22 21 20 19 XIN/CLKIN 25 1 18 BCLK1 X2 2 BCLK1 17 9SQL4952 VDDXTAL3.3 3 16 VDDA3.3 connect epad vSADR/REF3.3 4 GNDA 15 to GND GNDREF 5 14 BCLK0 GNDDIG 613BCLK0 7 8 9 10 11 12 24-pin VFQFPN, 4x4 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table + Read/Write Bit SADR Address x State of SADR on first application 0 1101000 of CKPWRGD PD 1 1101010 x 3 Power Management Table SMBus BCLKx CKPWRGD PD REF OE bit True O/P Comp. O/P 1 1 2 0X Low Low Hi-Z 1 1 Running Running Running 1 1 11 Running Disabled Disabled 1 1 4 10 Disabled Disabled Disabled 1. The output state is set by B11 1:0 (Low/Low default) 2. REF is Hi-Z until the 1st assertion of CKPWRGD PD high. After this, when CKPWRG PD is low, REF is disabled unless Byte3 5 =1, in which case REF is running.. 3. Input polarities defined at default SMBus values. 4. See SMBus description for Byte 3, bit 4 Power Connections Pin Number Description VDD GND 35,24 XTAL, REF 76 Digital Power 11,20 10,21,25 BCLK outputs 16 15 PLL Analog 2-OUTPUT CK420BQ DERIVATIVE 2 DECEMBER 12, 2016 VDDDIG3.3 GNDXTAL SCLK 3.3 vSS EN tri SDATA 3.3 CKPWRGD PD GND GND VDD3.3 VDD3.3 vOE0 vOE1