4-output CK420BQ Derivative 9SQL4954 DATASHEET Description Features/Benefits The 9SQL4954 is a member of IDT s Lite family of server Direct connection to 85 transmission lines saves 16 2 clocks. It generates 4 100MHz outputs that exceed the resistors and 27mm compared to standard HCSL requirements of the CK420BQ CPU/SRC clocks. Each output 142mW typical power consumption eases thermal has its own OE pin for clock management and supports 2 concerns 1/10 the power of CK420BQ different spread spectrum levels in addition to spread off. It Contains default configuration SMBus interface not also provides a copy of the 25MHz internal XO. The required for device operation 9SQL4954 supports PCIe Common Clock (CC) and OE pins support BCLK power management Independent Reference Clock (IR) architectures. 25MHz input frequency standard crystal frequency Recommended Application 25MHz REF output eliminates XO from boar Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF PCIe Gen1, Gen2, Gen3, Gen4 Server Clock outputs minimize EMI and phase jitter for each application Output Features BCLK outputs blocked until PLL is locked clean system start-up 4 -100MHz Low-power HCSL (LP-HCSL) CPU/SRC pairs Two selectable SMBus addresses multiple devices can Integrated terminations for 85 Zout easily share an SMBus segment 1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL) Space saving 32-pin 5x5mm VFQFPN minimal board support space Key Specifications BCLK outputs: Cycle-to-cycle jitter <50ps Output-to-output skew <50ps PCIe Gen1, Gen2, Gen3, Gen4 CC compliant PCIe Gen2, Gen3 IR compliant QPI/UPI compliant SAS12G compliant (SSC off) 12k-20M phase jitter <2ps rms (SSC off) REF output: Phase jitter <200fs rms (SSC off) 50ppm frequency accuracy on all clocks Block Diagram y REF vOE(3:0) 4 XIN/CLKIN 25 BCLK3 X2 BCLK2 SSC Capable BCLK1 PLL vSADR BCLK0 vSS EN tri CKPWRGD PD Control Logic SDATA 3.3 SCLK 3.3 9SQL4954 DECEMBER 12, 2016 1 2016 Integrated Device Technology, Inc.9SQL4954 DATASHEET Pin Configuration 32 31 30 29 28 27 26 25 GNDXTAL 1 24 vOE2 XIN/CLKIN 25 2 23 BCLK2 X2 3 BCLK2 22 9SQL4954 VDDXTAL3.3 4 VDDA3.3 21 connect VDDREF3.3 5 20 GNDA epad to GND vSADR/REF3.3 6 BCLK1 19 GNDREF 7 BCLK1 18 GNDDIG 817vOE1 9 10111213141516 32-pin VFQFPN, 5x5 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table + Read/Write Bit SADR Address x State of SADR on first application 0 1101000 of CKPWRGD PD 1 1101010 x Power Management Table SMBus OEx BCLKx CKPWRGD PD REF OE bit Pin True O/P Comp. O/P 1 1 2 0X X Low Low Hi-Z 1 1 0 Running Running Running 1 1 11 1 Running Disabled Disabled 1 1 4 10 X Disabled Disabled Disabled 1. The output state is set by B11 1:0 (Low/Low default) 2. REF is Hi-Z until the 1st assertion of CKPWRGD PD high. After this, when CKPWRG PD is low, REF is disabled unless Byte3 5 =1, in which case REF is running.. 3. Input polarities defined at default SMBus values. 4. See SMBus description for Byte 3, bit 4 Power Connections Pin Number Description VDD GND 41 XTAL Analog 57 REF Output 98, 30 Digital Power 16, 25 15, 26, 33 BCLK outputs 21 20 PLL Analog 4-OUTPUT CK420BQ DERIVATIVE 2 DECEMBER 12, 2016 VDDDIG3.3 vSS EN tri SCLK 3.3 CKPWRGD PD SDATA 3.3 GND vOE0 vOE3 BCLK0 BCLK3 BCLK0 BCLK3 GND GND VDDO3.3 VDDO3.3