2:12 Low Power Differential 9ZML1232 Z-Buffer Mux for PCIe, UPI and PFT Datasheet Description Features The 9ZML1232 is a 2-input/12-output differential mux for 25MHz to 100MHz ZDB mode supports PFT clock delay use in servers. It meets the demanding DB1200ZL management performance specifications and utilizes Low-Power 9 selectable SMBus addresses multiple devices can HCSL-compatible outputs to reduce power consumption share same SMBus segment and termination components. It is suitable for PCI-Express Separate VDDIO for outputs allows maximum power Gen13 or QPI/UPI applications, and uses a fixed external savings feedback to maintain low drift for demanding QPI PLL or bypass mode PLL can dejitter incoming clock applications. Hardware or software-selectable PLL BW minimizes jitter peaking in downstream PLLs Applications Spread spectrum compatible tracks spreading input Clock Mux for Servers clock for EMI reduction SMBus interface unused outputs can be disabled Output Features Differential outputs are Low/Low in power down 12 Low-Power (LP) HCSL Output Pairs maximum power savings Key Specifications Cycle-to-cycle jitter < 50ps Output-to-output skew < 65ps Input-to-output delay: Fixed at 0ps Input-to-output delay variation < 50ps Phase jitter: PCIe Gen3 < 1ps rms Phase jitter: QPI/UPI 9.6GB/s < 0.2ps rms Block Diagram OE(11:0) FBOUT NC Z-PLL DIF INB (SS Compatible) DIF INB DIF(11:0) DIF INA DIF INA HIBW BYPM LOBW SEL A B CKPWRGD/PD Logic SMB A0 tri SMB A1 tri SMBDAT SMBCLK 2021 Renesas Electronics Corporation 1 January 22, 2021 OE3 OE2 GND VDDIO DIF 3 DIF 3 DIF 2 DIF 2 VDD GND DIF 1 DIF 1 DIF 0 DIF 0 GND VDDIO OE1 OE0 9ZML1232 Datasheet Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 OE7 VDDA 1 54 OE6 GNDA 2 53 VDDIO SEL A B 3 52 GND vHIBW BYPM LOBW 4 51 DIF 7 CKPWRGD PD 5 50 DIF 7 DIF INB 6 49 DIF 6 DIF INB 7 48 DIF 6 GND 8 47 GND VDDR 9 46 9ZML1232 VDD DIF INA 10 45 DIF 5 DIF INA 11 44 DIF 5 vSMB A0 tri 12 43 DIF 4 SMBDAT 13 42 DIF 4 SMBCLK 14 41 VDDIO vSMB A1 tri 15 40 GND GND 16 39 OE5 FBOUT NC 17 38 OE4 FBOUT NC 18 37 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 prefix indicates internal 120Kohm Pull Up v prefix indicates internal 120Kohm Pull down 10mm x 10mm 72-MLF, 0.5mm pin pitch Power Management Table Inputs Outputs Control Bits PLL State DIF IN/ SMBus DIFx/ FBOUT NC/ CKPWRGD PD DIF IN EN bit DIFx FB OUT NC 0 X X Low/Low Low/Low OFF 0 Low/Low Running ON 1 Running 1 Running Running ON PLL Operating Mode Table Tri-Level Input Thresholds Level Voltage HiBW BypM LoBW Byte0, bit (7:6) Low <0.8V Low ( PLL Low BW) 00 Mid 1.2<Vin<1.8V Mid (Bypass) 01 High Vin > 2.2V High (PLL High BW) 11 NOTE: PLL is off in Bypass mode 9ZML1232 SMBus Addressing Power Connections SMB A(1:0) tri SMBus Address (Rd/Wrt bit = 0) 00 D8 Pin Number Description 0M DA VDD VDDIO GND 01 DE 12 Analog PLL M0 C2 98 Analog Input MM C4 16, 22, 27, 34, 21, 33, 40, M1 C6 28, 45, 64 39, 46, 51, 58, DIF clocks 52, 57, 69 10 CA 63, 70 1M CC 11 CE 2021 Renesas Electronics Corporation 2 January 22, 2021 OE11 OE10 GND VDDIO DIF 11 DIF 11 DIF 10 DIF 10 VDD GND DIF 9 DIF 9 DIF 8 DIF 8 GND VDDIO OE9 OE8