9ZML1253EKILF Renesas

2:12 DB1200ZL Derivative for 9ZML1233E/9ZML1253E PCIe Gen1-4 and UPI Datasheet Description Features SMBus write lock feature increases system security The 9ZML1233E/9ZML1253E are second generation enhanced performance DB1200ZL derivatives. The parts are pin-compatible 2 software-configurable input-to-output delay lines manage upgrades to the 9ZML1232B, while offering much improved phase transport delay for complex topologies jitter performance. A fixed external feedback maintains low drift for 2 LP-HCSL outputs eliminate 24 resistors, save 41mm of area critical QPI/UPI applications, while each input channel has (1233E) software adjustable input-to-output delay to ease transport delay LP-HCSL outputs with 85 Zout eliminate 48 resistors, save management for today s more complex server topologies. The 2 82mm of area (1253E) 9ZML1233E and 9ZML1253E have an SMBus Write Lockout pin 12 OE pins hardware control of each output for increased device and system security. 3 selectable SMBus addresses multiple devices can share same SMBus segment PCIe Clocking Architectures Selectable PLL bandwidths minimizes jitter peaking in Common Clocked (CC) cascaded PLL topologies Independent Reference (IR) with and without spread spectrum Hardware/SMBus control of PLL bandwidth and bypass change mode without power cycle Typical Applications Spread spectrum compatible tracks spreading input clock for EMI reduction Servers 100MHz PLL Mode UPI support Storage 10 x 10 mm 72-VFQFPN package small board footprint Networking SSDs Key Specifications Cycle-to-cycle jitter < 50ps Output Features Output-to-output skew < 50ps 12 Low-Power (LP) HCSL output pairs (1233E) Input-to-output delay: 0ps default 12 Low-Power (LP) HCSL output pairs with 85 Zout (1253E) Input-to-output delay variation < 50ps Phase jitter: PCIe Gen4 < 0.5ps rms Phase jitter: UPI > 9.6GB/s < 0.1ps rms Phase jitter: IF-UPI < 1.0ps rms Block Diagram FBOUT NC I2O Low Phase Noise Delay FBOUT NC Z-PLL SEL A B (SS-Compatible) DIF 11 DIF INA DIF 11 DIF INA Bypass path 12 DIF INB outputs DIF INB vHIBW BYPM LOBW CKPWRGD PD vSMB A0 tri DIF 0 vSMB WRTLOCK DIF 0 NOTE: Internal series resistors are only SMBDAT present on the 9ZML1253 SMBCLK OE(11:0) 2021 Renesas Electronics Corporation 1 R31DS0024EU1000 May 12, 2021 CONTROL9ZML1233E/9ZML1253E Datasheet Contents Description 1 PCIe Clocking Architectures . 1 Typical Applications . 1 Output Features 1 Features 1 Key Specifications 1 Block Diagram . 1 Pin Assignments 3 Pin Descriptions 3 Absolute Maximum Ratings . 6 Electrical Characteristics . 6 Clock Periods . 15 General SMBus Serial Interface Information . 16 How to Write . 16 9ZML1233E/9ZML1253E SMBus Addressing . 16 How to Read . 16 Package Outline Drawings . 20 Ordering Information . 20 Revision History . 21 2021 Renesas Electronics Corporation 2 R31DS0024EU1000 May 12, 2021