DATASHEET 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI 9ZX21201 General Description Features/Benefits The IDT9ZX21201 is a 12-output DB1200Z suitable for PCI-Express Space-saving 64-pin packages Gen3 or QPI applications. The part is backwards compatible to Fixed feedback path/ 0ps input-to-output delay PCIe Gen1 and Gen2. A fixed external feedback maintains low drift for critical QPI applications. In bypass mode, the IDT9ZX21201 can 9 Selectable SMBus Addresses/Mulitple devices can share provide outputs up to 150MHz. the same SMBus Segment 12 OE pins/Hardware control of each output Recommended Application PLL or bypass mode/PLL can dejitter incoming clock 12-output PCIe Gen3/ QPI differential buffer for Romley and newer 100MHz or 133MHz PLL mode operation/supports PCIe platforms and QPI applications Selectable PLL bandwidth/minimizes jitter peaking in Key Specifications downstream PLL s Cycle-to-cycle jitter <50ps Spread Spectrum Compatible/tracks spreading input clock Output-to-output skew < 65 ps for low EMI Input-to-output delay variation <50ps Software control of PLL Bandwidth and Bypass Settings/ PLL can dejitter incoming clock (B Rev only) PCIe Gen3 phase jitter < 1.0ps RMS QPI 9.6GT/s 12UI phase jitter < 0.2ps RMS Output Features 12 - 0.7V differential HCSL output pairs Functional Block Diagram OE(11:0) DFB OUT Z-PLL DIF(11:0) (SS Compatible) DIF IN DIF IN HIBW BYPM LOBW 100M 133M CKPWRGD/PD SMB A0 tri Logic SMB A1 tri SMBDAT SMBCLK IREF Note: Even though the feedback is fixed, DFB OUT still needs a termination network for the part to function. IDT 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D - 11/19/15 19ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDDA GND 148 GNDA DIF 7 247 IREF DIF 7 346 100M 133M vOE7 445 HIBW BYPM LOBW vOE6 544 CKPWRGD PD DIF 6 643 GND742 DIF 6 VDDR GND 841 9ZX21201 DIF IN VDD 940 DIF IN DIF 5 10 39 SMB A0 tri DIF 5 11 38 SMBDAT vOE5 12 37 SMBCLK vOE4 13 36 SMB A1 tri DIF 4 14 35 DFB OUT DIF 4 15 34 DFB OUT GND 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Notes: Pins with prefix have internal ~100K pullup Pins with v prefix have internal ~100K pulldown. Tri-level Input Thresholds Level Voltage MLF Power Connections <0.8V Low Pin Number Mid 1.2<Vin<1.8V Description High Vin > 2.2V VDD VDD GND 1 2 Analog PLL Functionality at Power Up (PLL Mode) 8 7 Analog Input DIF IN 23,33,41,48, 100M 133M DIF 24,40,57 25,32,49,56 DIF clocks (MHz) 58 1 100.00 DIF IN 0 133.33 DIF IN 9ZX21201 SMBus Addressing Pin SMBus Address PLL Operating Mode Readback Table (Rd/Wrt bit = 0) SMB A1 tri SMB A0 tri HiBW BypM LoBW Byte0, bit 7 Byte 0, bit 6 0 D8 0 Low (Low BW) 0 0 0M DA Mid (Bypass) 0 1 1 High (High BW) 1 1 0 DE M0 C2 PLL Operating Mode M C4 M HiBW BypM LoBW MODE M 1 C6 Low PLL Lo BW 0 1 CA Mid Bypass 1 M CC 11 CE High PLL Hi BW NOTE: PLL is OFF in Bypass Mode IDT 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15 2 DIF 0 DIF 11 DIF 0 DIF 11 vOE0 vOE11 vOE1 vOE10 DIF 1 DIF 10 DIF 1 DIF 10 GND GND VDD VDD VDD VDD DIF 2 DIF 9 DIF 2 DIF 9 vOE2 vOE9 vOE3 vOE8 DIF 3 DIF 8 DIF 3 DIF 8 VDD VDD