DATASHEET FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI 9ZX21501C Description Features/Benefits The 9ZX21501C is a 15-output version of the Intel Fixed feedback path 0ps input-to-output delay DB1900Z Differential Buffer suitable for PCI-Express Gen3 9 Selectable SMBus addresses multiple devices can or QPI applications. The part is backwards compatible to share same SMBus segment PCIe Gen1 and Gen2. A fixed external feedback maintains 7 dedicated OE pins hardware control of outputs low drift for critical QPI applications. In bypass mode, the PLL or bypass mode PLL can dejitter incoming clock 9ZX21501C can provide outputs up to 400MHz. Selectable PLL BW minimizes jitter peaking in downstream PLL s Recommended Application Spread spectrum compatible tracks spreading input 15-output PCIe Gen3/QPI buffer with fixed feedback for clock for EMI reduction Romley platforms SMBus Interface unused outputs can be disabled Output Features 100MHz & 133.33MHz PLL mode legacy QPI support 15 - 0.7V current mode differential HCSL output pairs Undriven differential outputs in Power Down mode for maximum power savings Key Specifications Cycle-to-cycle jitter: <50ps Output-to-output skew: <65ps Input-to-output delay: Fixed at 0 ps Input-to-output delay variation: <50ps Phase jitter: PCIe Gen3 <1ps rms Phase jitter: QPI 9.6GB/s <0.2ps rms Functional Block Diagram 7 OE(5 8,10 12) DFB OUT Z-PLL (SS Compatible) DIF(14:0) DIF IN DIF IN HIBW BYPM LOBW 100M 133M CKPWRGD/PD SMB A0 tri Logic SMB A1 tri SMBDAT SMBCLK IREF IDT FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI 1 9ZX21501C REV F 0416139ZX21501C FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 IREF 1 48 OE11 100M 133M 2 47 DIF 11 HIBW BYPM LOBW 3 46 DIF 11 CKPWRGD PD 4 45 OE10 GND 5 44 DIF 10 VDDR 6 43 DIF 10 9ZX21501C DIF IN 7 42 NC NOTE: The DFB OUT pins must be DIF IN 8 41 VDD SMB A0 tri 9 40 GND terminated identically to the DIF SMBDAT 10 39 OE8 outputs SMBCLK 11 38 DIF 8 SMB A1 tri 12 37 DIF 8 NC 13 36 OE7 NC 14 35 DIF 7 DFB OUT 15 34 DIF 7 DFB OUT 16 33 OE6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Power Management Table Inputs Control Bits/Pins Outputs PLL DIF IN/ SMBus DIF(5:8,10:12)/ Other DIF/ DFB OUT/ State CKPWRGD/PD DIF IN EN bit OE Pin DIF(5:8,10:12) DIF DFB OUT 1 1 1 0X X X Hi-Z Hi-Z Hi-Z OFF 1 1 0X Running ON Hi-Z Hi-Z 1 Running 1 0 Running Running Running ON 1 Running 11 Running ON Hi-Z NOTE 1: Due to external pull down resistors, HI-Z results in Low/Low on the True/Complement outputs Functionality at Power-up (PLL mode) Power Connections Pin Number DIF IN DIF 100M 133M Description (MHz) MHz VDD GND 1 100.00 DIF IN 63 64 Analog PLL 0 133.33 DIF IN 6 5 Input Circuit 19, 27, 41, 52, 24, 40, 55 DIF clocks PLL Operating Mode 60 HiBW BypM LoBW MODE SMBus Addressing Low PLL Lo BW Mid Bypass Pin SMBus Address High PLL Hi BW SMB A1 tri SMB A0 tri (Rd/Wrt bit = 0) 0 D8 NOTE: PLL is OFF in Bypass Mode 0 0M DA 1 PLL Operating Mode Readback Table 0 DE M0 C2 HiBW BypM LoBW Byte0, bit 7 Byte 0, bit 6 M C4 M Low (Low BW) 0 0 1 M C6 Mid (Bypass) 0 1 1 0 CA High (High BW) 1 1 M 1 CC 11 CE Tri-Level Input Thresholds Level Voltage <0.8V Low Mid 1.2<Vin<1.8V High Vin > 2.2V IDT FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI 2 9ZX21501C REV F 041613 DIF 0 GNDA DIF 0 VDDA VDD DIF 17 DIF 1 DIF 17 DIF 1 VDD DIF 2 DIF 16 DIF 2 DIF 16 GND DIF 15 DIF 4 DIF 15 DIF 4 GND VDD DIF 13 DIF 5 DIF 13 DIF 5 VDD OE5 OE12 DIF 6 DIF 12 DIF 6 DIF 12