DATASHEET 9ZX21901B 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Description Features/Benefits The 9ZX21901 is a version of the Intel DB1900Z Differential Buffer External feedback path Adjustable input-to-output delay with an ajdustable external feedback path allowing the user to 9 Selectable SMBus addresses/ Multiple devices can eliminate trace delays from their design. It is suitable for PCIe Gen3 share same SMBus segment or QPI applications. The part is backwards compatible to PCIe 8 dedicated OE pins/ hardware control of outputs Gen1 and Gen2. The device maintains low drift for critical QPI applications. In bypass mode, the IDT9ZX21901 can provide outputs PLL or bypass mode/ PLL can dejitter incoming clock up to 400MHz. Selectable PLL BW/ minimizes jitter peaking in downstream PLL s Recommended Application Spread spectrum compatible/tracks spreading input clock 19 output PCIe Gen3/QPI buffer with adjustable feedback for Romley for EMI reduction platforms SMBus Interface/ unused outputs can be disabled Output Features 100MHz & 133.33MHz PLL mode/ Legacy QPI support 19 - 0.7V current mode differential HCSL output pairs Undriven differential outputs in Power Down mode for maximum power savings Key Specifications Cycle-to-cycle jitter: < 50ps Output-to-output skew: <65ps Input-to-output delay: User adjustable Input-to-output delay variation: <50ps Phase jitter: PCIe Gen3 < 1ps rms Phase jitter: QPI 9.6GB/s < 0.2ps rms Functional Block Diagram 8 OE(5 12) DFB OUT DIF IN DIF IN Z-PLL DIF(18:0) (SS Compatible) DFB IN DFB IN HIBW BYPM LOBW 100M 133M CKPWRGD/PD SMB A0 tri Logic SMB A1 tri SMBDAT SMBCLK IREF IDT 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1586P - 11/19/15 1DIF 6 DIF 6 OE5 DIF 5 DIF 5 VDD DIF 4 DIF 4 DIF 3 DIF 3 GND DIF 2 DIF 2 DIF 1 DIF 1 VDD DIF 0 DIF 0 9ZX21901B 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 OE11 VDDA 1 54 DIF 11 GNDA 2 53 DIF 11 IREF 3 52 OE10 100M 133M 4 51 DIF 10 HIBW BYPM LOBW 5 50 DIF 10 CKPWRGD PD 6 49 OE9 GND 7 48 DIF 9 VDDR 8 47 DIF 9 DIF IN 9 46 9ZX21901B VDD DIF IN 10 45 GND SMB A0 tri 11 44 OE8 SMBDAT 12 43 DIF 8 SMBCLK 13 42 DIF 8 SMB A1 tri 14 41 OE7 DFB IN 15 40 DIF 7 DFB IN 16 39 DIF 7 DFB OUT 17 38 OE6 DFB OUT 18 37 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72-pin MLF PLL Operating Mode Readback Table Power Connections Pin Number HiBW BypM LoBW Byte0, bit 7 Byte 0, bit 6 Description Low (Low BW) 0 0 VDD GND Mid (Bypass) 0 1 1 2 Analog PLL High (High BW) 1 1 8 7 Analog Input 21, 31, 45, Functionality at Power Up (PLL Mode) 26, 44, 63 DIF clocks 58, 68 DIF IN DIF 100M 133M (MHz) (MHz) 9ZX21901 SMBus Addressing 1 100.00 DIF IN Pin SMBus Address 0 133.33 DIF IN SMB A1 tri SMB A0 tri (Rd/Wrt bit = 0) 0 D8 PLL Operating Mode 0 0M DA HiBW BypM LoBW MODE 1 0 DE Low PLL Lo BW M0 C2 Mid Bypass M M C4 High PLL Hi BW 1 M C6 NOTE: PLL is OFF in Bypass Mode 0 1 CA Tri-level Input Thresholds M 1 CC Level Voltage 11 CE <0.8V Low Mid 1.2<Vin<1.8V High Vin > 2.2V IDT 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1586P - 11/19/15 2 DIF 18 DIF 18 DIF 17 DIF 17 VDD DIF 16 DIF 16 DIF 15 DIF 15 GND DIF 14 DIF 14 DIF 13 DIF 13 VDD OE12 DIF 12 DIF 12