19-Output Differential Zbuffer for PCIe Gen2/3 9ZX21901C and QPI DATASHEET General Description Features/Benefits The 9ZX21901 is Intel DB1900Z Differential Buffer suitable for Fixed feedback path/ 0ps input-to-output delay PCI-Express Gen3 or QPI applications. The part is backwards 9 Selectable SMBus addresses Multiple devices can share compatible to PCIe Gen1 and Gen2. A fixed external feedback same SMBus segment maintains low drift for critical QPI applications. In bypass 8 dedicated OE pins hardware control of outputs mode, the 9ZX21901 can provide outputs up to 400MHz. PLL or bypass mode PLL can dejitter incoming clock Selectable PLL BW minimizes jitter peaking in downstream Recommended Application PLL s 19-output PCIe Gen3/QPI buffer with fixed feedback for Spread spectrum compatible tracks spreading input clock Romley platforms for EMI reduction Output Features SMBus Interface unused outputs can be disabled 100MHz & 133.33MHz PLL mode legacy QPI support 19 0.7V current mode differential HCSL output pairs Undriven differential outputs in Power Down mode for Key Specifications maximum power savings Cycle-to-cycle jitter: < 50ps Output-to-output skew: <65ps Input-to-output delay: Fixed at 0 ps Input-to-output delay variation: <50ps Phase jitter: PCIe Gen3 < 1ps rms Phase jitter: QPI 9.6GB/s < 0.2ps rms Functional Block Diagram OE(12:5) 8 DFB OUT Z-PLL (SS DIF IN Compatible) DIF IN DIF(18:0) Bypass path HIBW BYPM LOBW 100M 133M CKPWRGD/PD SMB A0 tri Logic SMB A1 tri SMBDAT SMBCLK IREF Note: Even though the feedback is fixed, DFB OUT still needs a termination network for the part to function. 9ZX21901C REVISION N 11/19/15 1 2015 Integrated Device Technology, Inc.DIF 6 DIF 6 OE5 DIF 5 DIF 5 VDD DIF 4 DIF 4 DIF 3 DIF 3 GND DIF 2 DIF 2 DIF 1 DIF 1 VDD DIF 0 DIF 0 9ZX21901C DATASHEET Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 OE11 VDDA 1 54 DIF 11 GNDA 2 53 DIF 11 IREF 3 52 OE10 100M 133M 4 51 DIF 10 HIBW BYPM LOBW 5 50 DIF 10 CKPWRGD PD 6 49 OE9 GND 7 48 DIF 9 VDDR 8 47 9ZX21901C DIF 9 DIF IN 9 46 NOTE: DFB OUT pins must be terminated identically VDD DIF IN 10 45 to the regular DIF outputs GND SMB A0 tri 11 44 OE8 SMBDAT 12 43 DIF 8 SMBCLK 13 42 DIF 8 SMB A1 tri 14 41 OE7 NC 15 40 DIF 7 NC 16 39 DIF 7 DFB OUT 17 38 OE6 DFB OUT 18 37 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72-pin VFQFPN Functionality at Power Up (PLL Mode) Power Connections DIF IN DIF x Pin Number 100M 133M Description (MHz) (MHz) VDD GND 1 100.00 DIF IN 12 Analog PLL 0 133.33 DIF IN 8 7 Analog Input 21, 31, 45, 26, 44, 63 DIF clocks 58, 68 PLL Operating Mode Readback Table HiBW BypM LoBW Byte0, bit 7 Byte 0, bit 6 Low (Low BW) 0 0 9ZX21901 SMBus Addressing Mid (Bypass) 0 1 Pin SMBus Address High (High BW) 1 1 SMB A1 tri SMB A0 tri (Rd/Wrt bit = 0) 0 D8 0 0M DA PLL Operating Mode 1 0 DE HiBW BypM LoBW MODE M0 C2 Low PLL Lo BW M M C4 Mid Bypass 1 M C6 High PLL Hi BW 0 1 CA NOTE: PLL is OFF in Bypass Mode M 1 CC 11 CE Tri-level Input Thresholds Level Voltage Low <0.8V Mid 1.2<Vin<1.8V High Vin > 2.2V 19-OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI 2 REVISION N 11/19/15 DIF 18 DIF 18 DIF 17 DIF 17 VDD DIF 16 DIF 16 DIF 15 DIF 15 GND DIF 14 DIF 14 DIF 13 DIF 13 VDD OE12 DIF 12 DIF 12