9ZXL04x1E/9ZXL06x1E/ 4 to 12-Output Buffers for PCIe 9ZXL08x1E/9ZXL12x1E Gen15 and UPI Datasheet Description Features 412 Low-power HCSL (LP-HCSL) outputs The 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E family of Zero-Delay/Fanout Buffers (ZDB, FOB) are 2nd-generation Integrated terminations eliminate up to 4 resistors per output enhanced performance buffers for PCIe and CPU applications. pair The family meets all published QPI/UPI, DB2000Q and PCIe Dedicated OE pins support PCIe CLKREQ function Gen15 jitter specifications. Devices range from 4 to 12 outputs, Up to 9 selectable SMBus addresses (9ZXL12) with each output having an OE pin to support the PCIe Selectable PLL bandwidths minimizes jitter peaking in CLKREQ function for low power states. All devices meet cascaded PLL topologies DB2000Q, DB1200ZL and DB800ZL jitter and skew requirements. Hardware/SMBus control of ZDB and FOB modes PCIe Clocking Architectures Spread-spectrum compatible Common Clocked (CC) 1400MHz FOB operation (all devices) Independent Reference (IR) with and without spread spectrum 100MHz and 133.33MHz ZDB mode (9ZXL12, 9ZXL08) (SRIS, SRNS) 100MHz ZDB mode (9ZXL06, 9ZXL04) -40C to +85C operating temperature range (all devices) Key Specifications -40C to +105C operating temperature range (9ZXL08) Fanout Buffer Mode additive phase jitter: Package information: see Ordering Information for details PCIe Gen5 CC < 24s RMS DB2000Q additive jitter < 40s RMS Typical Applications QPI/UPI 11.4GB/s < 40fs RMS Servers/High-performance Computing IF-UPI additive jitter < 70fs RMS nVME Storage ZDB Mode phase jitter: Networking PCIe Gen5 CC < 22fs RMS Accelerators QPI/UPI 11.4GB/s < 120fs RMS Industrial Control IF-UPI additive jitter < 130fs RMS Cycle-to-cycle jitter < 50ps Output-to-output skew < 50 ps Block Diagram VDDR VDDA VDD VDDIO (9ZXL12x1 only) FBOUT NC FBOUT NC PLL DIF IN DIFn DIF IN DIFn 9ZXL12x1 9ZXL08x1 only 100M 133M 12, 8, 6, or 4 9ZXL12x1 only vSADR1 tri SMBus Factory outputs vSADR0 tri 9ZXL12x1 Engine Configuration 9ZXL0451 SMBCLK only SMBDAT DIF0 vHIBW BYPM-LOBW DIF0 CKPWRGD PD Control Logic vOE n:0 Series resistors are integrated on 9ZXLxx51 devices and external on 9ZXLxx31 devices GNDA GND 2020 Renesas Electronics Corporation 1 August 25, 20209ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Contents Description 1 PCIe Clocking Architectures . 1 Key Specifications 1 Features 1 Typical Applications . 1 Block Diagram . 1 Pin Assignments 3 9ZXL0451E Pin Assignment 3 9ZXL06x1E Pin Assignment 4 9ZXL08x1E Pin Assignment 5 9ZXL12x1E Pin Assignment 6 Pin Descriptions 7 Absolute Maximum Ratings 10 Thermal Characteristics . 10 Electrical Characteristics 11 Power Management 19 Test Loads . 20 General SMBus Serial Interface Information . 22 How to Write . 22 How to Read . 22 Package Outline Drawings . 26 Marking Diagrams . 26 9ZXL04x1 . 26 9ZXL06x1 . 27 9ZXL08x1 (industrial temperature range) . 27 9ZXL08x1 (extended temperature range) . 28 9ZXL12x1 . 28 Ordering Information . 29 Revision History . 31 2020 Renesas Electronics Corporation 2 August 25, 2020