DATASHEET 8-OUTPUT DB800ZL 9ZXL0831 General Description Features/Benefits The 9ZXL0831 is a low-power 8-output differential buffer Low-power push-pull outputs Save power and board that meets all the performance requirements of the Intel space - no Rp DB800ZL specification. It is suitable for PCI-Express Space-saving 48-pin VFQFPN package Gen1/2/3 or QPI/UPI applications, and uses a fixed external Fixed feedback path for 0ps input-to-output delay feedback to maintain low drift for demanding QPI/UPI 8 OE pins hardware control of each output applications. PLL or bypass mode PLL can dejitter incoming clock 100MHz or 133MHz PLL mode operation supports PCIe Recommended Application and QPI applications Buffer for Romley, Grantley and Purley Servers, SSD drives Selectable PLL bandwidth minimizes jitter peaking in and PCIe downstream PLL s Output Features Spread Spectrum Compatible tracks spreading input clock for low EMI 8 - LP-HCSL Output Pairs Key Specifications Cycle-to-cycle jitter <50ps Output-to-output skew <65 ps Input-to-output delay variation <50ps PCIe Gen3 phase jitter <1.0ps RMS QPI/UPI 9.6GT/s 12UI phase jitter <0.2ps RMS Block Diagram OE(7:0) DFB OUT NC Z-PLL (SS Compatible) DIF IN DIF(7:0) DIF IN HIBW BYPM LOBW 100M 133M CKPWRGD/PD Logic SMBDAT SMBCLK IDT 8-OUTPUT DB800ZL 1 9ZXL0831 REV E 0816169ZXL0831 8-OUTPUT DB800ZL Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 1 CKPWRGD PD 36 DIF 6 2 GND DIF 6 35 3 VDDR VDD 34 4 DIF IN 33 DIF 5 DIF IN 5 DIF 5 32 9ZXL0831 6 SMBDAT vOE5 31 Paddle is 7 SMBCLK vOE4 pin 49 30 8 DFB OUT NC Connect to GND 29 DIF 4 DFB OUT NC 9 DIF 4 28 VDD VDD 10 27 vOE0 11 26 DIF 3 NC 12 25 DIF 3 13 14 15 16 17 18 19 20 21 22 23 24 48-pin VFQFPN, 6x6 mm, 0.4mm pitch Power Management Table PLL STATE IF NOT IN DIF IN/ SMBus DIF(7:0)/ BYPASS CKPWRGD PD DIF IN EN bit DIF(7:0) MODE 0 X X Low/Low OFF 0 Low/Low ON 1 Running 1 Running ON Functionality at Power-up (PLL mode) PLL Operating Mode Readback Table DIF IN HiBW BypM LoBW Byte0, bit 7 Byte 0, bit 6 100M 133M DIF(7:0) Low (Low BW) 0 0 MHz 1 100.00 DIF IN Mid (Bypass) 0 1 0 133.33 DIF IN High (High BW) 1 1 Power Connections Tri-Level Input Thresholds Pin Number Level Voltage Description <0.8V Low VDD GND Mid 1.2<Vin<1.8V 44 49 Analog PLL High Vin > 2.2V 3 2 Analog Input 10,15,19, 49 DIF clocks 27,34,38, 42 PLL Operating Mode HiBW BypM LoBW MODE SMBus Address Low PLL Lo BW Address + Read/Write bit Mid Bypass 1101100 x High PLL Hi BW NOTE: PLL is OFF in Bypass Mode IDT 8-OUTPUT DB800ZL 2 9ZXL0831 REV E 081616 DIF 0 HIBW BYPM LOBW DIF 0 100M 133M NC VDD NC DIF 1 DIF 1 VDDA vOE1 NC VDD VDD vOE7 NC DIF 2 DIF 7 DIF 7 DIF 2 VDD vOE2 vOE3 vOE6