DATASHEET 12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI 9ZXL1230 General Description Features/Benefits The 9ZXL1230 is a small-footprint, low power 12-output Low-power push-pull outputs Save power and board differential buffer that meets all the performance space - no Rp requirements of the Intel DB1900Z specification. It is pin Pin compatible to 9ZX21200 easy path to >50% power compatible to the 9ZX21200. The 9ZXL1230 is backwards savings compatible to PCIe Gen2 and QPI 6.4GT/s specifications. A Space-saving 56-pin QFN package fixed, internal feedback path maintains low drift for critical Fixed feedback path for 0ps input-to-output delay QPI applications. 9 Selectable SMBus Addresses Mulitple devices can share the same SMBus Segment Recommended Application 4 OE pins Hardware control of four outputs, other 12-output Low Power PCIe Gen3/QPI differential buffer for outputs free run Romley PLL or bypass mode PLL can dejitter incoming clock 100MHz or 133MHz PLL mode operation supports PCIe Output Features and QPI applications 12 - 0.7V low-power HCSL-compatible output pairs Selectable PLL bandwidth minimizes jitter peaking in downstream PLL s Spread Spectrum Compatible tracks spreading input clock for low EMI Key Specifications Cycle-to-cycle jitter <50ps Output-to-output skew <65 ps Input-to-output delay variation <50ps PCIe Gen3 phase jitter <1.0ps RMS QPI 9.6GT/s 12UI phase jitter <0.2ps RMS Block Diagram OE(8,6,4,2) DFB OUT NC Z-PLL DIF(11:0) (SS Compatible) DIF IN DIF IN HIBW BYPM LOBW 100M 133M CKPWRGD/PD SMB A0 tri Logic SMB A1 tri SMBDAT SMBCLK IDT 12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI 1 9ZXL1230 REV C 1120159ZXL1230 12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI Pin Configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 GNDA 1 GND NC241 DIF 7 100M 133M 340 DIF 7 HIBW BYPM LOBW vOE6 439 CKPWRGD PD 538 DIF 6 GND 37 DIF 6 6 VDDR736 GND 9ZXL1230 DIF IN835 VDD DIF IN DIF 5 934 SMB A0 tri DIF 5 10 33 SMBDAT vOE4 11 32 SMBCLK 12 31 DIF 4 SMB A1 tri 13 30 DIF 4 DFB OUT NC 14 29 GND 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Note: Pins with prefix have internal 120K pullup Pins with v prefix have internal 120K pulldowm Power Management Table PLL STATE IF NOT IN DIF IN/ SMBus DIF(11:0)/ BYPASS CKPWRGD PD DIF IN EN bit DIF(11:0) MODE 0X XLow/LowOFF 0Low/Low ON 1 Running 1 Running ON Functionality at Power-up (PLL mode) DIF IN 100M 133M DIF(11:0) MHz 1 100.00 DIF IN 0 133.33 DIF IN Power Connections Pin Number Description VDD VDDIO GND 56 1 Analog PLL 7 6 Analog Input 20,29,36,42, 21,35,50 22,28,43,49 DIF clocks 51 IDT 12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI 2 9ZXL1230 REV C 112015 DFB OUT NC VDDA DIF 0 DIF 11 DIF 0 DIF 11 DIF 1 DIF 10 DIF 1 DIF 10 GND GND VDD VDD VDDIO VDDIO DIF 2 DIF 9 DIF 2 DIF 9 vOE2 vOE8 DIF 3 DIF 8 DIF 3 DIF 8 VDDIO VDDIO