12-output DB1200ZL 9ZXL1231 DATASHEET General Description Features/Benefits The 9ZXL1231 meets the demanding requirements of the Low-power push-pull HCSL outputs eliminate 24 resistors, 2 Intel DB1200ZL specification, including the critical low-drift save 41mm of area requirements of Intel CPUs. Pin compatible to 9ZX21201 easy path to >50% power savings Space-saving 64 VFQFPN package Recommended Application Fixed feedback path for 0ps input-to-output delay Buffer for Romley, Grantley and Purley Servers, solid state 9 Selectable SMBus Addresses multiple devices can storage and PCIe share the same SMBus Segment 12 OE pins hardware control of each output Output Features PLL or bypass mode PLL can dejitter incoming clock 12 - Low-Power (LP) HCSL output pairs Selectable PLL bandwidth minimizes jitter peaking in downstream PLL s Key Specifications Spread Spectrum Compatible tracks spreading input clock for low EMI Cycle-to-cycle jitter <50ps Output-to-output skew <50 ps Input-to-output delay variation <50ps PCIe Gen3 phase jitter <1.0ps RMS Phase jitter: QPI/UPI >=9.6GB/s <0.2ps rms Block Diagram OE(11:0) DFB OUT NC Z-PLL DIF(11:0) (SS Compatible) DIF IN DIF IN HIBW BYPM LOBW 100M 133M CKPWRGD/PD SMB A0 tri Logic SMB A1 tri SMBDAT SMBCLK 9ZXL1231 REVISION J 05/25/16 1 2016 Integrated Device Technology, Inc.9ZXL1231 DATASHEET Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDDA GND 148 GNDA DIF 7 247 NC DIF 7 346 100M 133M 445 vOE7 HIBW BYPM LOBW vOE6 544 CKPWRGD PD DIF 6 643 GND DIF 6 742 VDDR GND 849ZXL12311 DIF IN VDD 940 connect epad to ground DIF IN DIF 5 10 39 SMB A0 tri DIF 5 11 38 SMBDAT 12 37 vOE5 SMBCLK vOE4 13 36 SMB A1 tri DIF 4 14 35 DFB OUT NC DIF 4 15 34 DFB OUT NC GND 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9x9mm 64-pin VFQFPN Note: Pins with prefix have internal 120K pullup Pins with v prefix have internal 120K pulldowm Power Management Table PLL STATE IF NOT IN DIF IN/ SMBus DIF(11:0)/ BYPASS CKPWRGD PD DIF IN EN bit DIF(11:0) MODE 0X XLow/LowOFF 0Low/Low ON 1 Running 1Running ON Functionality at Power-up (PLL mode) Power Connections DIF IN Pin Number 100M 133M DIF(11:0) Description MHz VDD VDDIO GND 1 100.00 DIF IN 12 Analog PLL 0 133.33 DIF IN 8 7 Analog Input 24,40,57 25,32,49,56 23,33,41,48,58 DIF clocks 12-OUTPUT DB1200ZL 2 REVISION J 05/25/16 DIF 0 DIF 11 DIF 0 DIF 11 vOE0 vOE11 vOE1 vOE10 DIF 1 DIF 10 DIF 1 DIF 10 GND GND VDD VDD VDDIO VDDIO DIF 2 DIF 9 DIF 2 DIF 9 vOE2 vOE9 vOE3 vOE8 DIF 3 DIF 8 DIF 3 DIF 8 VDDIO VDDIO