12-Output DB1200ZL Derivative 9ZXL1251 with Integrated 85 Terminations Datasheet Description Features The 9ZXL1251 meets the demanding requirements of the 25MHz PFT clock delay management Intel DB1200ZL specification, including the critical low-drift 85 Low-power push-pull HCSL outputs eliminate 24 2 requirements of Intel CPUs. It is pin compatible to the resistors, save 41mm of area 9ZXL1231 and integrates 24 termination resistors, saving Pin compatible to 9ZX21201 and 9ZXL1231 easy path to 2 41mm board area. power and area savings Space-saving 64-pin VFQFPN package Applications Fixed feedback path for 0ps input-to-output delay Buffer for Romley, Grantley and Purley Servers, solid state 9 selectable SMBus addresses multiple devices can share storage and PCIe the same SMBus segment 12 OE pins hardware control of each output PLL or bypass mode supports common and separate clock Output Features architectures 12 LP-HCSL Output Pairs w/integrated terminations Selectable PLL bandwidth minimizes jitter peaking in (Zo = 85) downstream PLLs Spread spectrum compatible tracks spreading input clock Key Specifications for low EMI Cycle-to-cycle jitter < 50ps -40C to +85C device available supports demanding Output-to-output skew < 50ps environmental applications Input-to-output delay variation < 50ps PCIe Gen3 phase jitter < 1.0ps RMS Phase jitter: QPI/UPI > = 9.6GB/s < 0.2ps rms Block Diagram OE(11:0) DFB OUT NC Z-PLL (SS Compatible) DIF IN DIF(11:0) DIF IN HIBW BYPM LOBW 100M 133M CKPWRGD/PD SMB A0 tri Logic SMB A1 tri SMBDAT SMBCLK 2021 Renesas Electronics Corporation 1 January 28, 20219ZXL1251 Datasheet Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDDA 1 48 GND GNDA 2 DIF 7 47 NC 3 46 DIF 7 100M 133M 4 vOE7 45 vHIBW BYPM LOBW 5 vOE6 44 CKPWRGD PD 6 43 DIF 6 GND 7 DIF 6 42 9ZXL1251 VDDR 8 GND 41 connect epad (pin 65) DIF IN 9 40 VDD to ground DIF IN DIF 5 10 39 vSMB A0 tri DIF 5 11 38 SMBDAT vOE5 12 37 SMBCLK vOE4 13 36 vSMB A1 tri DIF 4 14 35 DFB OUT NC DIF 4 15 34 DFB OUT NC GND 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9 x 9mm VFQFPN package Note: Pins with prefix have internal 120K pullup Pins with v prefix have internal 120K pulldowm Pins with v prefix have internal 120K pullup/pulldown (biased to VDD/2) Power Management Table PLL STATE IF NOT IN DIF IN/ SMBus DIF(11:0)/ BYPASS CKPWRGD PD DIF IN EN bit DIF(11:0) MODE 0 X X Low/Low OFF 0 Low/Low ON 1 Running 1 Running ON Functionality at Power-up (PLL mode) DIF IN 100M 133M DIF(11:0) MHz 1100.00 DIF IN 0133.33 DIF IN Power Connections Pin Number Description VDD VDDIO GND 1 2 Analog PLL 8 7 Analog Input 23,33,41,48, 24,40,57 25,32,49,56 DIF clocks 58,65 2021 Renesas Electronics Corporation 2 January 28, 2021 DIF 0 DIF 11 DIF 0 DIF 11 vOE0 vOE11 vOE1 vOE10 DIF 1 DIF 10 DIF 1 DIF 10 GND GND VDD VDD VDDIO VDDIO DIF 2 DIF 9 DIF 2 DIF 9 vOE2 vOE9 vOE3 vOE8 DIF 3 DIF 8 DIF 3 DIF 8 VDDIO VDDIO