15-output DB1900Z Low-Power Derivative 9ZXL1550 DATASHEET Description Features/Benefits The 9ZXL1550 is a DB1900Z derivative buffer utilizing LP-HCSL outputs up to 90% IO power reduction, better Low-Power HCSL (LP-HCSL) outputs to increase edge rates signal integrity over long traces on long traces, reduce board space, and reduce power Direct connect to 85 transmission lines eliminates 60 2 consumption more than 50% from the original 9ZX21501. It is termination resistors, saves 103mm area pin-compatible to the 9ZXL1530 and has the output Pin compatible to the 9ZXL1530 easy upgrade to reduced terminations integrated. It is suitable for PCI-Express board space Gen1/2/3 or QPI/UPI applications, and uses a fixed external 64-VFQFPN package smallest 15 output Z-buffer feedback to maintain low drift for demanding QPI/UPI Fixed feedback path: ~ 0ps input-to-output delay applications. 9 Selectable SMBus addresses multiple devices can share same SMBus segment Recommended Application Separate VDDIO for outputs allows maximum power Buffer for Romley, Grantley and Purley Servers savings PLL or bypass mode PLL can dejitter incoming clock Key Specifications 100MHz & 133.33MHz PLL mode legacy QPI/UPI support Selectable PLL BW minimizes jitter peaking in downstream Cycle-to-cycle jitter: < 50ps PLL s Output-to-output skew: <75ps Spread spectrum compatible tracks spreading input clock Input-to-output delay variation: <50ps for EMI reduction Phase jitter: PCIe Gen3 < 1ps rms SMBus Interface unused outputs can be disabled Phase jitter: QPI 9.6GB/s < 0.2ps rms Output Features 15 - LP-HCSL Differential Output Pairs w/integrated terminations (Zo = 85 ) Block Diagram FBOUT NC Z-PLL (SS Compatible) DIF IN DIF(14:0) DIF IN HIBW BYPM LOBW 100M 133M CKPWRGD/PD SMB A0 tri Logic SMB A1 tri SMBDAT SMBCLK 9ZXL1550 REVISION E 11/20/15 1 2015 Integrated Device Technology, Inc.GND VDDIO DIF4 DIF4 DIF3 DIF3 VDD GND DIF2 DIF2 DIF1 DIF1 GND VDDIO DIF0 DIF0 9ZXL1550 DATASHEET Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDDA VDDIO 148 GNDA GND 247 100M 133M DIF9 346 HIBW BYPM LOBW DIF9 445 CKPWRGD PD 544 DIF8 GND DIF8 643 VDDR GND 742 9ZXL1550 DIF IN VDD 841 DIF IN DIF7 940 EPAD is Pin 65 SMB A0 tri 10 39 DIF7 SMBDAT DIF6 11 38 SMBCLK DIF6 12 37 SMB A1 tri VDDIO 13 36 FBOUT NC GND 14 35 FBOUT NC 15 34 DIF5 GND DIF5 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9x9 mm 64-pin VFQFPN Note: Pins with prefix have internal 120K pullup Pins with v prefix have internal 120K pulldowm Power Management Table Inputs Outputs Control Bits DIF IN/ SMBus DIFx/ FBOUT NC/ PLL State CKPWRGD PD DIF IN EN bit DIFx FBOUT NC 0 X X Low/Low Low/Low OFF 0 Low/Low Running ON 1 Running 1 Running Running ON Power Connections PLL Operating Mode Pin Number HiBW BypM LoBW Byte0, bit (7:6) Description Low ( PLL Low BW) 00 VDD VDDIO GND 12 Analog PLL Mid (Bypass) 01 7 6 Analog Input High (PLL High BW) 11 16,20,25,32, NOTE: PLL is off in Bypass mode 19,31,36,48,5 26, 41, 58 35,42,47,52, DIF clocks 1,63 57,64 Tri-Level Input Thresholds Level Voltage Functionality at Power-up (PLL mode) Low <0.8V DIF IN DIFx Mid 1.2<Vin<1.8V 100M 133M (MHz) (MHz) High Vin > 2.2V 1 100.00 DIF IN 0 133.33 DIF IN 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 2 REVISION E 11/20/15 GND VDDIO DIF14 DIF14 DIF13 DIF13 VDD GND DIF12 DIF12 DIF11 DIF11 GND VDDIO DIF10 DIF10