DATASHEET DG401, DG403 FN3284 Rev 11.00 Monolithic CMOS Analog Switches Nov 20, 2006 The DG401 and DG403 monolithic CMOS analog switches Features have TTL and CMOS compatible digital inputs. ON Resistance (Max) . 45 These switches feature low analog ON resistance (<45 ) Low Power Consumption (P ) .<35W D and fast switch time (t <150ns). Low charge injection ON Fast Switching Action simplifies sample and hold applications. -t (Max) . 150ns ON The improvements in the DG401, DG403 series are made -t (Max) 100ns OFF possible by using a high voltage silicon-gate process. An Low Charge Injection epitaxial layer prevents the latch-up associated with older DG401 Dual SPST Same Pinout as HI-5041 CMOS technologies. The 44V maximum voltage range permits controlling 30V signals. Power supplies may be DG403 Dual SPDT DG190, IH5043, IH5151, HI-5051 P-P single-ended from +5V to +34V, or split from 5V to 17V. TTL, CMOS Compatible The analog switches are bilateral, equally matched for AC or Single or Split Supply Operation bidirectional signals. The ON resistance variation with analog Pb-Free Plus Anneal Available (RoHS Compliant) signals is quite low over a 15V analog input range. The three different devices provide the equivalent of two SPST (DG401) Applications or two SPDT (DG403) relay switch contacts with CMOS or Audio Switching TTL level activation. The pinout is similar, permitting a standard layout to be used, choosing the switch function as Battery Operated Systems needed. Data Acquisition Hi-Rel Systems Pinouts DG401 Sample and Hold Circuits (16 LD SOIC, TSSOP) Communication Systems TOP VIEW Automatic Test Equipment D 1 16 S 1 1 NC 2 15 IN 1 Ordering Information NC 3 14 V- PART PART TEMP. PKG. NC 4 13 GND NUMBER* MARKING RANGE (C) PACKAGE DWG. NC 5 12 V L DG401DY* DG401DY -40 to +85 16 Ld SOIC M16.15 NC 6 11 V+ DG401DYZ* DG401DYZ -40 to +85 16 Ld SOIC M16.15 IN NC 7 10 2 (Note) (Pb-free) D 8 9 S 2 2 DG401DVZ* DG401 DVZ -40 to +85 16 Ld TSSOP M16.173 (Note) (Pb-free) DG403DY* DG403DY -40 to +85 16 Ld SOIC M16.15 DG403 DG403DYZ* DG403DYZ -40 to +85 16 Ld SOIC M16.15 (16 LD SOIC, TSSOP) (Note) (Pb-free) TOP VIEW DG403DVZ* DG403 DVZ -40 to +85 16 Ld TSSOP M16.173 D 1 16 S 1 1 (Note) (Pb-free) NC 2 15 IN 1 *Add -T suffix for tape and reel. D 3 14 V- 3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free S 4 13 GND material sets molding compounds/die attach materials and 100% 3 matte tin plate termination finish, which are RoHS compliant and S 5 12 V 4 L compatible with both SnPb and Pb-free soldering operations. Intersil V+ D 6 11 4 Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of 10 IN NC 7 2 IPC/JEDEC J STD-020. 9 S D 8 2 2 NOTE: (NC) No Connection. FN3284 Rev 11.00 Page 1 of 12 Nov 20, 2006DG401, DG403 TRUTH TABLE DG401 DG403 LOGIC SWITCH SWITCH 1, 2 SWITCH 3, 4 0OFF OFF ON 1ON ON OFF NOTE: Logic 0 0.8V. Logic 1 2.4V. Functional Diagrams DG401 DG403 V V+ V V+ L L 12 11 12 11 16 1 16 1 S D S D 1 1 1 1 4 3 S D 3 3 15 15 IN IN 1 1 10 10 IN IN 2 2 9 8 9 8 S D S D 2 2 2 2 5 6 S D 4 4 13 14 13 14 GND V- GND V- SWITCHES SHOWN FOR LOGIC 1 INPUT Schematic Diagram V+ SOURCE V- V L V IN V+ GND DRAIN V- FN3284 Rev 11.00 Page 2 of 12 Nov 20, 2006