HCTS541DMSR Renesas

DATASHEET HCTS541MS FN3073 Rev 1.00 Radiation Hardened Non-Inverting Octal Buffer/Line Driver, Three-State August 1995 Features Pinouts 20 LEAD CERAMIC DUAL-IN-LINE 3 Micron Radiation Hardened CMOS SOS METAL SEAL PACKAGE (SBDIP) Total Dose 200K RAD (Si) MIL-STD-1835 CDIP2-T20 TOP VIEW 2 SEP Effective LET No Upsets: >100 MEV-cm /mg 1 20 VCC -9 OE1 Single Event Upset (SEU) Immunity < 2 x 10 Errors/ A0 2 OE2 19 Bit-Day (Typ) A1 3 18 Y0 12 Dose Rate Survivability: >1 x 10 RAD (Si)/s A2 4 17 Y1 10 Dose Rate Upset >10 RAD (Si)/s 20ns Pulse A3 5 16 Y2 A4 6 15 Y3 Latch-Up Free Under Any Conditions A5 7 14 Y4 Fanout (Over Temperature Range) A6 8 13 Y5 - Bus Driver Outputs - 15 LSTTL Loads A7 9 12 Y6 o o Military Temperature Range: -55 C to +125 C GND 10 11 Y7 Significant Power Reduction Compared to LSTTL ICs DC Operating Voltage Range: 4.5V to 5.5V LSTTL Input Compatibility - VIL = 0.8V Max 20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) - VIH = VCC/2 Min MIL-STD-1835 CDFP4-F20 Input Current Levels Ii 5A at VOL, VOH TOP VIEW OE1 120 VCC Description A0 2 19 OE2 A1 3 18 Y0 The Intersil HCTS541MS is a Radiation Hardened non- A2 4 17 Y1 inverting octal buffer/line driver, three-state outputs. The A3 5 16 Y2 output enable pins (OEN1 and OEN2) control the three-state outputs. If either enable is high the outputs will be in the high A4 6 15 Y3 impedance state. For data output both enables (OEN1 and A5 7 14 Y4 OEN2) must be low. A6 8 13 Y5 A7 9 12 Y6 The HCTS541MS utilizes advanced CMOS/SOS technology GND 10 11 Y7 to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS54 is supplied in a 20 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE o o HCTS541DMSR -55 C to +125 C Intersil Class S Equivalent 20 Lead SBDIP o o HCTS541KMSR -55 C to +125 C Intersil Class S Equivalent 20 Lead Ceramic Flatpack o HCTS541D/Sample +25 C Sample 20 Lead SBDIP o HCTS541K/Sample +25 C Sample 20 Lead Ceramic Flatpack o HCTS541HMSR +25CDie Die FN3073 Rev 1.00 Page 1 of 10 August 1995HCTS541MS Functional Block Diagram VDD P P TTL P 2 N P 18 N N N OE TTL 3 17 VDD TTL TTL P 4 16 = P N TTL 5 15 TTL 6 14 TTL 7 13 TTL 8 12 TTL 1 OE 19 TTL TRUTH TABLE INPUTS OE1 OE2 An OUTPUTS LL H H HX X Z XHX Z LLLL H = High Voltage Level, L = Low Voltage Level, X = Immaterial, Z = High Impedance FN3073 Rev 1.00 Page 2 of 10 August 1995