DATASHEET HFA3101 FN3663 Rev 5.00 Gilbert Cell UHF Transistor Array September 2004 The HFA3101 is an all NPN transistor array configured as a Features Multiplier Cell. Based on Intersils bonded wafer UHF-1 SOI Pb-free Available as an Option process, this array achieves very high f (10GHz) while T maintaining excellent h and V matching characteristics High Gain Bandwidth Product (f ) . 10GHz FE BE T that have been maximized through careful attention to circuit High Power Gain Bandwidth Product 5GHz design and layout, making this product ideal for Current Gain (h ) . 70 communication circuits. For use in mixer applications, the FE cell provides high gain and good cancellation of 2nd order Low Noise Figure (Transistor) . 3.5dB distortion terms. Excellent h and V Matching FE BE Ordering Information Low Collector Leakage Current <0.01nA PART NUMBER TEMP. PKG. Pin to Pin Compatible to UPA101 (BRAND) RANGE (C) PACKAGE DWG. Applications HFA3101B -40 to 85 8 Ld SOIC M8.15 (H3101B) Balanced Mixers HFA3101BZ -40 to 85 8 Ld SOIC M8.15 Multipliers (H3101B) (Note) (Pb-free) Demodulators/Modulators HFA3101B96 -40 to 85 8 Ld SOIC Tape M8.15 (H3101B) and Reel Automatic Gain Control Circuits HFA3101BZ96 -40 to 85 8 Ld SOIC Tape M8.15 Phase Detectors (H3101B) (Note) and Reel (Pb-free) Fiber Optic Signal Processing NOTE: Intersil Pb-free products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin Wireless Communication Systems plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL Wide Band Amplification Stages classified at Pb-free peak reflow temperatures that meet or exceed Radio and Satellite Communications the Pb-free requirements of IPC/JEDEC J STD-020C. High Performance Instrumentation Pinout HFA3101 (SOIC) TOP VIEW Q Q Q Q 1 2 3 4 Q Q 6 5 NOTE: Q and Q - 2 Paralleled 3 m x 50m Transistors 5 6 Q , Q , Q , Q - Single 3 m x 50 m Transistors 1 2 3 4 FN3663 Rev 5.00 Page 1 of 12 September 2004 1 8 2 7 3 6 4 5HFA3101 Absolute Maximum Ratings Thermal Information o V , Collector to Emitter Voltage 8.0V Thermal Resistance (Typical, Note 1) ( C/W) CEO JA V , Collector to Base Voltage . 12.0V CBO SOIC Package . 185 o V , Emitter to Base Voltage . 5.5V EBO Maximum Junction Temperature (Die) 175 C o I , Collector Current 30mA C Maximum Junction Temperature (Plastic Package) 150 C o o Maximum Storage Temperature Range . -65 C to 150 C o Operating Conditions Maximum Lead Temperature (Soldering 10s) .300 C (SOIC - Lead Tips Only) o o Temperature Range -40 C to 85 C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. is measured with the component mounted on an evaluation PC board in free air. JA o Electrical Specifications T = 25 C A (NOTE 2) TEST PARAMETER TEST CONDITIONS LEVEL MIN TYP MAX UNITS Collector to Base Breakdown Voltage, V , Q thru I = 100 A, I = 0 A 12 18 - V (BR)CBO 1 C E Q 6 Collector to Emitter Breakdown Voltage, V , I = 100 A, I = 0 A 8 12 - V (BR)CEO C B Q and Q 5 6 Emitter to Base Breakdown Voltage, V , Q thru Q I = 10 A, I = 0 A 5.5 6 - V (BR)EBO 1 6 E C Collector Cutoff Current, I , Q thru Q V = 8V, I = 0 A - 0.1 10 nA CBO 1 4 CB E Emitter Cutoff Current, I , Q and Q V = 1V, I = 0 A - - 200 nA EBO 5 6 EB C DC Current Gain, h , Q thru Q I = 10mA, V = 3V A 40 70 - FE 1 6 C CE Collector to Base Capacitance, C Q thru Q V = 5V, f = 1MHz C - 0.300 - pF CB 1 4 CB Q and Q - 0.600 - pF 5 6 Emitter to Base Capacitance, C Q thru Q V = 0, f = 1MHz B - 0.200 - pF EB 1 4 EB Q and Q - 0.400 - pF 5 6 Current Gain-Bandwidth Product, f Q thru Q I = 10mA, V = 5V C - 10 - GHz T 1 4 C CE Q and Q I = 20mA, V = 5V C - 10 - GHz 5 6 C CE Power Gain-Bandwidth Product, f Q thru Q I = 10mA, V = 5V C - 5 - GHz MAX 1 4 C CE Q and Q I = 20mA, V = 5V C - 5 - GHz 5 6 C CE Available Gain at Minimum Noise Figure, G , I = 5mA, f = 0.5GHz C - 17.5 - dB NFMIN C Q and Q V = 3V 5 6 CE f = 1.0GHz C - 11.9 - dB Minimum Noise Figure, NF , Q and Q I = 5mA, f = 0.5GHz C - 1.7 - dB MIN 5 6 C V = 3V CE f = 1.0GHz C - 2.0 - dB 50 Noise Figure, NF , Q and Q I = 5mA, f = 0.5GHz C - 2.25 - dB 50 5 6 C V = 3V CE f = 1.0GHz C - 2.5 - dB DC Current Gain Matching, h /h , Q and Q , I = 10mA, V = 3V A 0.9 1.0 1.1 FE1 FE2 1 2 C CE Q and Q , and Q and Q 3 4 5 6 Input Offset Voltage, V , (Q and Q ), (Q and Q ), I = 10mA, V = 3V A - 1.5 5 mV OS 1 2 3 4 C CE (Q and Q ) 5 6 Input Offset Current, I , (Q and Q ), (Q and Q ), I = 10mA, V = 3V A - 5 25 A C 1 2 3 4 C CE (Q and Q ) 5 6 o Input Offset Voltage TC, dV /dT, (Q1 and Q2, Q3 and Q , I = 10mA, V = 3V C - 0.5 - V/ C OS 4 C CE Q and Q ) 5 6 Collector to Collector Leakage, I V = 5V B - 0.01 - nA TRENCH-LEAKAGE TEST FN3663 Rev 5.00 Page 2 of 12 September 2004