DATASHEET HIP1020 FN4601 Rev 2.00 Single, Double or Triple-Output Hot Plug Controller July 2004 The HIP1020 applies a linear voltage ramp to the gates of Features any combination of 3.3V, 5V, and 12V MOSFETs. The Rise Time Controlled to Device-Bay Specifications internal charge pump doubles a 12V bias or triples a 5V bias No Additional Components Required to deliver the high-side drive capability required when using more cost-effective N-Channel MOSFETs. The 5V/ms ramp Internal Charge Pump Drives N-Channel MOSFETs rate is controlled internally and is the proper value to turn on Drives any Combination of One, Two or Three Outputs most devices within the Device-Bay-specified di/dt limit. If a Internally-Controlled Turn-On Ramp slower rate is required, the internally-determined ramp rate - Optional Capacitor Selects Slower Rates can be over ridden using an optional external capacitor. Prevents False Turn on During Hot Insertion When VCC = 12V, the charge pump ramps the voltage on Operates using 12V or 5V Bias HGATE from zero to 22V in about 4ms. This allows either a standard or a logic-level MOSFET to become fully enhanced Improves Device Bay Peripheral Size Cost and Complex- ity when used as a high-side switch for 12V power control. The voltage on LGATE ramps from zero to 16V allowing the - Minimal Component Count simultaneous control of 3.3V and/or 5V MOSFETs. - Tiny 5-Pin SOT23 Package Controls Standard and Logic-Level MOSFETs When VCC = 5V, the charge pump enters voltage-tripler mode. The voltage on HGATE ramps from zero to 12.5V in Compatible with TTL and 3.3V Logic Devices about 3ms while LGATE ramps to 12.0V. This mode is ideal Shutdown Current < 1A for control of high-side MOSFET switches used in 3.3V and Operating Current < 3mA 5V power switching when 12V bias is not available. Applications Ordering Information Device Bay Peripherals PART TEMP. PKG. o Hot Plug Control NUMBER RANGE ( C) PACKAGE DWG. Power Distribution Control HIP1020CK-T 0 to 70 5 Ld SOT23 T + R P5.064 HIP1020CKZ-T 0 to 70 5 Ld SOT23 T + R P5.064 Pinout (See Note) (Pb-free) HIP1020 (SOT23) NOTE: Intersil Pb-free products employ special Pb-free material sets molding TOP VIEW compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that VCC 1 5 EN meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. GND 2 LGATE 4 3 HGATE FN4601 Rev 2.00 Page 1 of 6 July 2004HIP1020 Typical Applications ENABLE HIP1020 ENABLE HIP1020 CHARGE 1 5 OPTIONAL PUMP CHARGE 1 5 OPTIONAL PUMP C1 2 C1 2 34 34 V V 12 12,OUT V V 5 5,OUT V V 5,OUT 5 V V 33,OUT 33 V V 33 33,OUT FIGURE 1A. DEVICE-BAY HOT PLUG CONTROLLER WITH FIGURE 1B. DEVICE-BAY HOT PLUG CONTROLLER WITH VCC = 12V VCC = 5V Pin Descriptions PIN SYMBOL FUNCTION DESCRIPTION 1 VCC Bias Supply Connect this pin to either a 12V or a 5V source. The HIP1020 detects the bias-voltage level at pin 1 and decides whether to operate as a voltage-doubler or a voltage-tripler. Consequently, it is not recommended to operate with bias voltages between 5V ( 10%) and 12V (10%). In the absence of an enable signal at pin 5, the current into pin 1 is less than 1 A. It is necessary for voltage to be present at pin 1 prior to applying an enable signal at pin 5. 2 GND Ground Connect to the negative rail of the supply that is connected to pin 1. 3 LGATE Gate Driver for the 5V When VCC = 12V, connect this pin to the gate(s) of the 5V and/or 3.3V MOSFETs. When VCC and/or 3.3V = 5V, connect this pin to the gate of a 3.3V MOSFET. Upon a rising edge on EN (pin 5), the MOSFET(s) voltage on this pin will ramp linearly to ~16V when VCC = 12V and ~12V when VCC = 5V. An internal dv/dt activated clamp shunts coupled noise to ground preventing unintended turn on at either output. The internal dv/dt-activated clamp also protects pin 5. 4 HGATE 12V or 5V MOSFET When VCC = 12V, connect this pin to the gate of the 12V MOSFET. When VCC = 5V, connect Gate Driver this pin to the gate of the 5V MOSFET. Upon a rising edge on EN (pin 5), the voltage on this pin will ramp linearly to ~22V when VCC = 12V and ~13V when VCC = 5V. 5 EN Enable Connect a TTL or 3.3V logic signal to this pin to control the outputs at pins 3 and 4. A rising edge on pin 5 initiates the linear voltage ramps at pins 3 and 4. Be sure that the device driving EN does not enter a high-impedance state when enabling is not desired and that its maximum rise time does not exceed 100 s. FN4601 Rev 2.00 Page 2 of 6 July 2004