100V, 2A Peak, High Frequency Half-Bridge Drivers with Adjustable Dead Time Control and PWM Input HIP2120, HIP2121 Features 9 Ld TDFN B Package Compliant with 100V Conductor The HIP2120 and HIP2121 are 100V, high frequency, half-bridge Spacing Guidelines per IPC-2221 MOSFET driver ICs. They are based on the popular ISL2100A and ISL2101A half-bridge drivers. Break-Before-Make Dead-Time Prevents Shoot-through and is adjustable up to 220ns These drivers have a programmable dead-time to insure break-before-make operation between the high-side and low-side Bootstrap Supply Max Voltage to 114VDC drivers. The dead-time is adjustable up to 250ns. Wide Supply Voltage Range (8V to 14V) A single PWM logic input controls both bridge outputs (HO, LO). An Supply Undervoltage Protection enable pin (EN), when low, drives both outputs to a low state. All CMOS Compatible Input Thresholds with Hysteresis (HIP2120) logic inputs are V tolerant and the HIP2120 has CMOS inputs DD with hysteresis for superior operation in noisy environments. 1.6 /1 Typical Output Pull-up/Pull-down Resistance On-Chip 1 Bootstrap Diode The HIP2120 has hysteretic inputs with thresholds that are proportional to V . The HIP2121 has 3.3V logic/TTL compatible DD Applications inputs. Telecom Half-Bridge DC/DC Converters Two package options are provided. The 10 Ld 4x4 DFN package has standard pinouts. The 9 Ld 4x4 DFN package omits pin 2 to comply UPS and Inverters with 100V conductor spacing per IPC-2221. Motor Drives Class-D Amplifiers Forward Converter with Active Clamp Related Literature FN7670 HIP2122, HIP2123 100V, 2A Peak, High Frequency Half-Bridge Driver with Delay Timers 200 100V max 160 HIP2120/21 140 HALF BRIDGE VDD HB 120 100 PWM SECONDARY HO CIRCUITS 80 PWM EN CONTROLLER HS 60 RDT FEEDBACK WITH VSS LO ISOLATION 40 EPAD 20 816 2432 404856 64 80 R (k) DT FIGURE 1. TYPICAL APPLICATION FIGURE 2. DEAD-TIME vs TIMING RESISTOR December 23, 2011 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Copyright Intersil Americas Inc. 2011. All Rights Reserved FN7668.0 Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. DEAD-TIME (ns)HIP2120, HIP2121 Block Diagram VDD HB HIP2120, UNDER HO LEVEL VOLTAGE SHIFT HIP2121 HS HIP2121 HIP2120/21 PWM DELAY UNDER RDT VOLTAGE Optional inversion for future part LO numbers DELAY VSS EN EPAD IS ELECTRICALLY ISOLATED HIP2121 HIP2120/21 EPAD Pin Configurations HIP2120, HIP2121 HIP2120, HIP2121 (10 LD 4X4 TDFN) (9 LD 4X4 TDFN) TOP VIEW TOP VIEW VDD 1 10 LO VDD 1 10 LO HB 2 9 VSS 9 VSS EPAD EPAD HO 3 8 PWM HB 3 8 PWM HS 4 7 EN HO 4 7 EN HS 5 6 RDT NC 5 6 RDT FN7668.0 2 December 23, 2011