DATASHEET HIP9011 FN4367 Rev 2.00 Engine Knock Signal Processor January 6, 2006 The HIP9011 is used to provide a method of detecting Features premature detonation often referred to as Knock or Ping in Two Sensor Inputs internal combustion engines. Microprocessor Programmable The IC is shown in the Simplified Block Diagram. The chip can select between one of two sensors, if needed for Accurate and Stable Filter Elements accurate monitoring or for V type engines. Internal control Digitally Programmable Gain via the SPI bus is fast enough to switch sensors between Digitally Programmable Time Constants each firing cycle. A programmable bandpass filter processes the signal from either of the sensor inputs. The Digitally Programmable Filter Characteristics bandpass filter can be selected to optimize the extraction On-Chip Crystal Oscillator the engine knock or ping signals from the engine background noise. Further single processing is obtained by Programmable Frequency Divider full wave rectification of the filtered signal and applying it to External Clock Frequencies up to 24MHz an integrator whose output voltage level is proportional to - 4, 5, 6, 8, 10, 12, 16, 20, and 24MHz the knock signal amplitude. The chip is under o o microprocessor control via a SPI interface bus. Operating Temperature Range -40 C to 125 C Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information TEMP. Applications PART PART RANGE PKG. o Engine Knock Detector Processor NUMBER MARKING ( C) PACKAGE DWG. HIP9011AB HIP9011AB -40 to 125 M20.3 20 Ld SOIC Analog Signal Processing Where Controllable Filter Characteristics are Required HIP9011ABZ HIP9011ABZ -40 to 125 M20.3 20 Ld SOIC (See Note) (Pb-free) Add T suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Simplified Block Diagram CH0FB CH0IN - CH0NI + PROGRAMMABLE PROGRAMMABLE OUTPUT PROGRAMMABLE GAIN BANDPASS ACTIVE DRIVER INTOUT INTEGRATOR CH1FB STAGE FULL WAVE FILTER AND 40 - 600 s 2 - 0.111 RECTIFIER SAMPLE 1-20kHz CH1IN 32 STEPS AND HOLD 64 STEPS 64 STEPS - CH1NI + OSCIN PROGRAMMABLE CLOCK OSCOUT DIVIDER TO SWITCHED CAPACITOR NETWORKS SCK CS POWER SUPPLY REGISTERS SI SPI AND AND INTERFACE SO BIAS CIRCUITS STATE MACHINE INT/HOLD VMID V GND DD TEST FN4367 Rev 2.00 Page 1 of 11 January 6, 2006 CHANNEL SELECT SWITCHES 3RD ORDER ANTIALIASING FILTERHIP9011 Pinout HIP9011 (SOIC) TOP VIEW V 1 20 CH0NI DD GND 2 19 CH0IN 3 18 CH0FB VMID INTOUT 4 17 CH1FB NC 5 16 CH1IN NC 6 15 CH1NI TEST INT/HOLD 7 14 8 13 CS SCK 9 12 OSCIN SI 10 11 OSCOUT SO Pin Descriptions PIN NUMBER DESIGNATION DESCRIPTION 1V Five volt power input. DD 2 GND This pin is tied to ground. 3V This pin is connected to the internal mid-supply generator and is brought out for bypassing by a 0.022F capacitor. MID 4 INTOUT Buffered output of the integrator. Output signal is held by an internal Sample and Hold circuit when INT/HOLD is low. 5, 6 NC These pins are not internally connected. Do Not Use. 7INT/HOLD Selects whether the chip is in the Integrate Mode (Input High) or in the Hold Mode (Input Low). This pin has an internal pull down. 8CS A low input on this pin enables the chip to communicate over the SPI bus. This pin has an internal pull-up. 9 OSCIN Input to inverter used for the oscillator circuit. A 4MHz crystal or ceramic resonator is connected between this pin and pin 10. To bias the inverter, a 1.0M to 10M resistor is usually connected between this pin and pin 10. 10 OSCOUT Output of the inverter used for the oscillator. See pin 9 above. 11 SO Output of the chip SPI data bus. This is a three-state output that is controlled via the SPI bus. The output is placed in the high impedance state by setting CS high when the chip is not selected. This high impedance state can also be programmed by setting the LSB of the prescaler word to 1. This will take precedence over CS. A 0 enables the active state. The Diagnostic Mode overrides these conditions. 12 SI Input of the chip SPI data bus. Data length is eight bits. This pin has an internal pull-up. 13 SCK Input from the SPI clock. Normally low, the data is transferred to the chip internal circuitry on the falling clock edge. This pin has an internal pull up. 14 TEST A low on this pin places the chip in the diagnostic mode. For normal operation this pin is tied high or left open. This pin has an internal pull up. 15 CH1NI Non-inverting input of Channel one. 16 CH1IN Inverting input to channel one amplifier. A resistor is tied from this summing input to the transducer. A second resistor is tied between this pin and pin 17, CH1FB to establish the gain of the amplifier. 17 CH1FB Output of the channel one amplifier. This pin is used to apply feedback. 18 CH0FB Output of the channel zero amplifier. This pin is used to apply feedback. 19 CH0IN Inverting input to channel zero amplifier. Remainder same as channel one amplifier except feedback is applied from pin 18. 20 CH0NI Non-inverting input of Channel 0. Remainder the same as pin 16, except feedback is applied from terminal 18. FN4367 Rev 2.00 Page 2 of 11 January 6, 2006