Single, Low Voltage Digitally Controlled Potentiometer (XDCP) ISL23315 Features 2 256 resistor taps The ISL23315 is a volatile, low voltage, low noise, low power, I C Bus , 256 Taps, single digitally controlled potentiometer (DCP), 2 I C serial interface which integrates DCP core, wiper switches and control logic on - No additional level translator for low bus supply a monolithic CMOS integrated circuit. - Two address pins allow up to four devices per bus The digitally controlled potentiometer is implemented with a Power supply combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the -V = 1.7V to 5.5V analog power supply CC 2 2 I C bus interface. The potentiometer has an associated -V = 1.2V to 5.5V I C bus/logic power supply LOGIC volatile Wiper Register (WR) that can be directly written to and Wiper resistance: 70 typical V = 3.3V read by the user. The contents of the WR controls the position CC of the wiper. When powered on, the ISL23315s wiper will Shutdown Mode - forces the DCP into an end-to-end open always commence at mid-scale (128 tap position). circuit and R is shorted to R internally W L The low voltage, low power consumption, and small package Power-on preset to mid-scale (128 tap position) of the ISL23315 make it an ideal choice for use in battery Shutdown and standby current <2.8A max operated equipment. In addition, the ISL23315 has a V LOGIC pin allowing down to 1.2V bus operation, independent from the DCP terminal voltage from 0V to V CC V value. This allows for low logic levels to be connected CC 10k, 50k or 100k total resistance directly to the ISL23315 without passing through a voltage level shifter. Extended industrial temperature range: -40C to +125C The DCP can be used as a three-terminal potentiometer or as a 10 Ld MSOP or 10 Ld TQFN packages two-terminal variable resistor in a wide variety of applications Pb-free (RoHS compliant) including control, parameter adjustments, and signal processing. Applications Power supply margining RF power amplifier bias compensation LCD bias compensation Laser diode bias compensation 10000 8000 6000 4000 2000 0 0 50 100 150 200 250 TAP POSITION (DECIMAL) FIGURE 2. V ADJUSTMENT FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP REF POSITION, 10k DCP August 15, 2011 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Copyright Intersil Americas Inc. 2010, 2011. All Rights Reserved FN7778.1 Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners RESISTANCE ()ISL23315 Block Diagram V V CC LOGIC R SCL H POWER-UP INTERFACE, SDA I/O LEVEL CONTROL WR A1 BLOCK SHIFTER AND VOLATILE STATUS A0 REGISTER LOGIC AND WIPER CONTROL CIRCUITRY R L R W GND Pin Configurations Pin Descriptions ISL23315 MSOP TQFN SYMBOL DESCRIPTION (10 LD MSOP) 2 110 V I C bus /logic supply. Range 1.2V to LOGIC TOP VIEW 5.5V 10 GND V 1 2 1 SCL Logic Pin - Serial bus clock input LOGIC 9 V SCL 2 CC 3 2 SDA Logic Pin - Serial bus data SDA 3 8 RH input/open drain output A0 4 7 RW 4 3 A0 Logic Pin - Hardwire slave address 2 A1 5 6 RL pin for I C serial bus. Range: V or GND LOGIC ISL23315 5 4 A1 Logic Pin - Hardwire slave address 2 (10 LD TQFN) pin for I C serial bus. TOP VIEW Range: V or GND LOGIC 6 5 RL DCP low terminal 7 6 RW DCP wiper terminal 8 7 RH DCP high terminal GND SCL 1 9 98 V Analog power supply. CC SDA V 2 8 CC Range 1.7V to 5.5V A0 RH 3 7 10 9 GND Ground pin A1 RW 4 6 FN7778.1 2 August 15, 2011 RL 5 10 V LOGIC