DATASHEET ISL45042 FN6072 Rev 9.00 LCD Module Calibrator Apr 13, 2011 The V voltage of an LCD panel needs to be adjusted to COM Features remove flicker. The ISL45042 can be used to digitally adjust 128-Step Adjustable Sink Current Output a panels V voltage by controlling its output sink current. COM The output of the ISL45042 is connected to an external 2.6V to 3.6V Digital Supply Voltage Operating Range voltage divider and an external V buffer amplifier. In this (3.0V Minimum Programming Voltage) COM application, the user can control the V voltage with 7-bit COM 4.5V to 20V Analog Supply Voltage Operating Range accuracy (128 steps). Once the desired V setting is COM (10.8V Minimum Programming Voltage) obtained, the settings can be stored in the non-volatile Rewritable EEPROM for Storing the Optimum V Value COM EEPROM memory, which would then be automatically recalled during every power-up. Output Adjustment Enable/Disable Control The V adjustment and non-volatile memory Output Guaranteed Monotonic Over-Temperature COM programming is through a single interface pin (CTL). Once Two Pin Adjustment, Programming and Enable the desired programmed value is obtained, the Counter Ultra Thin 8 Ld 3mmx3mm DFN (0.8mm Max) Enable pin (CE) can be used to prevent further adjustment or programming. Pb-Free (RoHS Compliant) The full-scale sink current of the ISL45042 is set using an Applications external resistor connected to the SET pin. The full-scale sink current determines the lowest voltage of the external LCD Panels voltage divider. Ordering Information The ISL45042 is available in an 8 Ld 3mmx3mm TDFN package with a maximum thickness of 0.8mm for ultra thin TEMP. PART NUMBER PART RANGE PACKAGE PKG. LCD panel design. (Notes 1, 2, 3) MARKING (C) (Pb-Free) DWG. Pinout ISL45042IRZ 042Z -40 to +85 8 Ld 3x3 TDFN L8.3x3A ISL45042 (8 LD TDFN) NOTES: TOP VIEW 1. Add -T* suffix for tape and reel. Please refer to TB347 for details on reel specifications. OUT 1 8 SET 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, AVDD 2 7 CE and 100% matte tin plate plus anneal (e3 termination finish, which DNC 3 6 CTL is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified GND 4 5 V DD at Pb-free peak reflow temperatures that meet or exceed the Pb- free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL45042. For more information on MSL please see techbrief TB363. FN6072 Rev 9.00 Page 1 of 9 Apr 13, 2011ISL45042 Pin Descriptions PIN FUNCTION OUT Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 128. See SET pin function in Pin Descriptions on page 2 for the maximum adjustable sink current setting. AVDD High-Voltage Analog Supply. Connects to top of external resistor divider to determine the V voltage. 10.8V to 20V for EEPROM COM programming, 4.5V to 20V normal operation (before/after programming). Bypass to GND with 0.1F de-coupling capacitor. DNC Do Not Connect. This pin may be left unconnected or tied to GND. Do not apply any non-zero voltages or signals to this pin. GND Ground connection. V Low-Voltage Digital Supply for digital logic. Typically 3V to 3.6V. Bypass to GND with 0.1F de-coupling capacitor. DD CTL Internal Counter Up/Down Control and Internal EEPROM Programming Control Input. If CE is high, a mid-to-low transition increments the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT. A mid-to-high transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage at OUT. Applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-bit counter. See EEPROM Programming section in Electrical Specifications table on page 4 for details. CE Counter Enable Pin with internal pull-down resistor. Connect CE to VDD to enable adjustment of the output sink current. Float or connect CE to GND to prevent further adjustment or programming. SET Maximum Sink Current Adjustment Point. Connect a resistor from the SET pin to GND to set the maximum adjustable sink current of the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET. Block Diagram ISL45042 CE AVDD 400k to IBIAS 5M UP IOUT DWN ANALOG DCP AND CTL DIGITAL INTERFACE PWRUP CURRENT OUTPUT UP/DOWN COUNTER WITH THRESHOLD BLOCK POR SENSORS WITH PRESET SET LATCHES PRGM READ PRGM MEMORY POR EEPROM OR PRGM NVL MEMORY GND VDD FN6072 Rev 9.00 Page 2 of 9 Apr 13, 2011