ISL5217 Data Sheet July 8, 2005 FN6004.3 Quad Programmable Up Converter Features The ISL5217 Quad Programmable UpConverter (QPUC) is a Output Sample Rates Up to 104MSPS with Input Data QASK/FM modulator/FDM upconverter designed for high Rates Up to 6.5MSPS dynamic range applications such as cellular basestations. The Processing Capable of >140dB SFDR Out of Band QPUC combines shaping and interpolation filters, a complex Vector modulation for supporting IS-136, EDGE, IS95, TD- modulator, and timing and carrier NCOs into a single package. SCDMA, CDMA-2000-1X/3X, W-CDMA, and UMTS Each QPUC can create four FDM channels. Multiple QPUCs can FM Modulation for Supporting AMPS, NMT, and GSM be cascaded digitally to provide for up to 16 FDM channels in Four Completely Independent Channels on Chip, Each With multi-channel applications. Programmable 256 Tap Shaping FIR, Half-Band, and High The ISL5217 supports both vector and FM modulation. In vector Order Interpolation Filters modulation mode, the QPUC accepts 16-bit I and Q samples to 16-Bit parallel Processor Interface and Four Independent generate virtually any quadrature AM or PM modulation format. Serial Data Inputs The QPUC also has two FM modulation modes. In the FM with Two 20-bit I/O Buses and Tw o 20-bit Output Buses Allow pulse shaping mode, the 16-bit frequency samples are pulse Cascading Multiple Devices shaped/bandlimited prior to FM modulation. No band limiting filter 32-Bit Programmable Carrier NCO 48-Bit Programmable follows the FM modulator. This FM mode is useful for GMSK type Symbol Timing NCOs modulation formats. In the FM with band limiting filter mode, the Dynamic Gain Profiling and Output Routing Control 16-bit frequency samples directly drive the FM modulator. The Pb-Free Plus Anneal Available (RoHS Compliant) FM modulator output is filtered to limit the spectral occupancy. Applications This FM mode is useful for analog FM or FSK modulation formats. Single or Multiple Channel Digital Software Radio The QPUC includes an NCO driven interpolation filter, which Transmitters (Wide-Band or Narrow-Band) allows the input and output sample rate to have an integer Base Station Transmitter and Smart Antennas and/or variable relationship. This re-sampling feature Operates with HSP50216 in Software Radio Solutions simplifies cascading modulators with sample rates that do not Compatible with the HI5960/ ISL5961 or HI5828/ISL5929 have harmonic or integer frequency relationships. D/A Converters The QPUC offers digital output spectral purity that exceeds Ordering Information 100dB at the maximum output sample rate of 104MSPS, for input sample rates as high as 6.5MSPS. PART TEMP PKG. DWG. o NUMBER RANGE ( C) PACKAGE A 16-bit microprocessor compatible interface is used to load configuration and baseband data. A programmable FIFO depth ISL5217KI -40 to 85 196 Ld BGA V196.15x15 interrupt simplifies the interface to the I and Q input FIFOs. ISL5217KIZ (Note) -40 to 85 196 Ld BGA (Pb-free) V196.15x15 ISL5217EVAL1 25 Evaluation Kit NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Block Diagram SDA I/Q I/Q I/Q I/Q I/Q I/Q SDB INPUT I0 HALF INTPL COMPLEX CAS IOUT(19:0) SHAPING Q0 DELAY SDC DATA 4 CH BAND FILTER MIXER SUM FILTER/ SDD SUM I1 SUM FM MOD. SIN COS Q1 CARRIER I2 CAS NCO Q2 QOUT(19:0) SUM SAMPLE I3 NCO CHANNEL 0 Q3 QIN(19:0) 1 IIN(19:0) CHANNEL 1 2 CHANNEL 2 3 CHANNEL 3 4 P<15:0> A<6:0> CONFIGURATION AND CONTROL BUS PARALLEL HOST INTERFACE CNTRL CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. GAIN PROFILE GAIN CONTROLISL5217 FN6004.3 2 July 8, 2005 Functional Block Diagram ISL5217 SCLKA FSRA SERIAL SDA I FM 18 FM / SDB INTERFACE 18 MOD. Q FM SDC / 20 21 I<21:0> HALF / / SDD I SF 20 COMPLEX 4 INPUT I IN<15:0> BAND 20 21 Q<21:0> / Q IN<15:0> SUMMER MIXER / / 1 / 16 SHAPING I FIFO / BYPASS / I IN<15:0> FILTER Q FIFO 16 / Q IN<15:0> CH ENABLE<0> SER. PAR. MOD. TYPE <1:0> FID<31:0> SR<47:0> COARSE CHANNEL FINE SAMPLE PHASE<3:0> INTPL PHASES<1:0> PHASE<11:0> ROUTING UP NCO PHASE OFFSET<1:0> CONTROL GAIN<11:0> INTERFACE GAIN PROFILE LENGTH<6:0> AND TIMING OUTPUT EN CARRIER CARRIER PHASE<15:0> CARRIER FREQUENCY<31:0> NCO DUALQUADMODE (CH0 AND CH2 ONLY) CHANNEL 0 I<21:0> 4 INPUT SCLKB Q<21:0> SUMMER FSRB CH EN<1> 2 CHANNEL 1 I<21:0> 4 INPUT SCLKC Q<21:0> CLK SUMMER FSRC CH EN<2> 3 A<6:0> CHANNEL 2 P<15:0> I<21:0> 4 INPUT SCLKD Q<21:0> SUMMER FSRD CH EN<3> 4 CHANNEL 3 TXENA ISTROBEUPDATE TXENB RESET ISTRB TXENC TXEND CASCADE DELAY<1:0> UPDA DEVICE ROUTEBUS<15:0> UPDB UPROCESSOR UPDC CASCADE IN ENABLE UPDD OUTPUTMODE<1:0> INTERFACE IOUT<19:0> WR OUTPUTMODE2X QOUT<19:0> RD I STROBE EN IIN<19:0> OUTPUT CS ISTROBEPOLARITY QIN<19:0> CONTROL RESET TRITST ENABLE BUS<7:0> RDMODE OUTEN<1:0> SYNCO TRITST OFFBIN TMS TDI JTAG TCK TDO TRST <4:0> TX ENABLE<3:0> UPDATE<3:0> CH SELECT<3:0> MUX ROUTEBUS UPDATE 1-7 DEEP FIFO MUX MUX LIMITER MUX GAIN PROFILE INTERPOLATION FILTER SIN<18:0> COS<18:0> GAIN CONTROL PROGRAMMABLE DELAY