NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-IN ERSIL r ww .inter l.com sc T o w si /t DATASHEET ISL6532A FN9099 Rev 6.00 ACPI Regulator/Controller for Dual Channel DDR Memory Systems Sep 12, 2013 The ISL6532A provides a complete ACPI compliant power Features solution for up to 4 DIMM dual channel DDR/DDR2 Memory Generates 3 Regulated Voltages systems. Included are both a synchronous buck controller - Synchronous Buck PWM Controller with Standby LDO and integrated LDO to supply V with high current during DDQ - 3A Integrated Sink/Source Linear Regulator with S0/S1 states and standby current during S3 state. During Accurate VDDQ/2 Divider Reference S0/S1 state, a fully integrated sink-source regulator - Glitch-free Transitions During State Changes generates an accurate (V /2) high current V voltage DDQ TT without the need for a negative supply. A buffered version of - LDO Regulator for 1.5V Video and Core voltage the V /2 reference is provided as V . An LDO DDQ REF ACPI Compliant Sleep State Control controller is also integrated for AGP core voltage regulation. Integrated V Buffer REF The switching PWM controller drives two N-Channel PWM Controller Drives Low Cost N-Channel MOSFETs MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltage- 250kHz Constant Frequency Operation mode control with fast transient response. Both the switching Tight Output Voltage Regulation regulator and standby LDO provide a maximum static - All Outputs: 2% Over-Temperature regulation tolerance of 2% over line, load, and temperature ranges. The output is user-adjustable by means of external 5V or 3.3V Down Conversion resistors down to 0.8V. Fully-Adjustable Outputs with Wide Voltage Range: Down to 0.8V supports DDR and DDR2 Specifications Switching memory core output between the PWM regulator and the standby LDO during state transitions is Simple Single-Loop Voltage-Mode PWM Control Design accomplished smoothly via the internal ACPI control Fast PWM Converter Transient Response circuitry. The NCH signal provides synchronized switching of Under and Overvoltage Monitoring on All Outputs a backfeed blocking switch during the transitions eliminating the need to route 5V Dual to the memory supply. OCP on the Switching Regulator An integrated soft-start feature brings all outputs into Integrated Thermal Shutdown Protection regulation in a controlled manner when returning to S0/S1 QFN Package Option state from any sleep state. During S0 the PGOOD signal - QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad indicates V is within spec and operational. TT Flat No Leads - Product Outline Each output is monitored for under and overvoltage events. - QFN Near Chip Scale Package Footprint Improves The switching regulator has overcurrent protection. Thermal PCB Efficiency, Thinner in Profile shutdown is integrated. Pb-free Available (RoHS Compliant) Ordering Information Applications TEMP. PART PART RANGE PKG. Single and Dual Channel DDR Memory Power Systems in NUMBER MARKING (C) PACKAGE DWG. ACPI compliant PCs , ISL6532ACR* ** ISL 6532ACR 0 to +70 28 Ld 6x6 QFN L28.6x6 Graphics Cards - GPU and Memory Supplies , ISL6532ACRZ* ** ISL6532 ACRZ 0 to +70 28 Ld 6x6 QFN L28.6x6 ASIC Power Supplies (Note) (Pb-free) Embedded Processor and I/O Supplies ISL6532AIRZ* ISL6532 AIRZ -40 to +85 28 Ld 6x6 QFN L28.6x6 (Note) (Pb-free) DSP Supplies *Add -T suffix for tape and reel. **Add -TK suffix for tape and reel. Please refer to TB347 for details on reel specifications NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN9099 Rev 6.00 Page 1 of 18 Sep 12, 2013ISL6532A Pinout ISL6532A (28 LD QFN) TOP VIEW 28 27 26 25 24 23 22 GNDP 1 21 PGOOD 5VSBY 2 20 PHASE 3 19 GNDQ DRIVE2 GND GNDQ 4 18 FB2 29 VTT 5 17 GNDA VTT 6 16 COMP VDDQ 7 15 FB 8 9 10 11 12 13 14 FN9099 Rev 6.00 Page 2 of 18 Sep 12, 2013 VDDQ GNDP VDDQ LGATE VTTSNS UGATE P5VSBY P12V OCSET S5 VREF OUT S3 VREF IN NCH