ISL6537ACRZ-T Renesas

DATASHEET ISL6537A FN9143 Rev 5.00 ACPI Regulator/Controller for Dual Channel DDR Memory Systems Jul 18, 2007 The ISL6537A provides a complete ACPI compliant power Features solution for up to 4 DIMM dual channel DDR/DDR2 Memory Generates 5 Regulated Voltages systems. Included are both a synchronous buck controller to - Synchronous Buck PWM Controller for DDR V supply V during S0/S1 and S3 states. During S0/S1 state, DDQ DDQ a fully integrated sink-source regulator generates an accurate - 3A Integrated Sink/Source Linear Regulator with (V /2) high current V voltage without the need for a Accurate VDDQ/2 Divider Reference for DDR V DDQ TT TT negative supply. A buffered version of the V /2 reference is DDQ - PWM Regulator for GMCH Core provided as V . A second PWM controller, which requires REF - LDO Regulator for CPU/GMCH V Termination TT external MOSFET drivers, is available for regulation of the - LDO Regulator for DAC GMCH Core voltage. An LDO controller is also integrated for the CPU V termination voltage regulation and the DAC. ACPI Compliant Sleep State Control TT The switching PWM controller drives two N-Channel Glitch-Free Transitions During State Changes MOSFETs in a synchronous-rectified buck converter Integrated V Buffer REF topology. The synchronous buck converter uses voltage- V PWM Controller Drives Low Cost N-Channel mode control with fast transient response. The switching DDQ MOSFETs regulator provides a maximum static regulation tolerance of 2% over line, load, and temperature ranges. The output is 250kHz Constant Frequency Operation user-adjustable by means of external resistors down to 0.8V. - Both PWM Controllers are Phase Shifted 180 An integrated soft-start feature brings all outputs into Tight Output Voltage Regulation regulation in a controlled manner when returning to S0/S1 - All Outputs: 2% Over Temperature state from any sleep state. During S0 the VIDPGD signal indicates that the GMCH and CPU V termination voltage Fully-Adjustable Outputs with Wide Voltage Range: Down TT is within spec and operational. to 0.8V Supports DDR and DDR2 Specifications Simple Single-Loop Voltage-Mode PWM Control Design All outputs, except VDAC, have undervoltage protection. The switching regulator also has overvoltage and Fast PWM Converter Transient Response overcurrent protection. Thermal shutdown is integrated. Under and Overvoltage Monitoring Pinout ISL6537A (6X6 QFN) OCP on the V Switching Regulator DDQ TOP VIEW Integrated Thermal Shutdown Protection Pb-Free Plus Anneal Available (RoHS Compliant) 28 27 26 25 24 23 22 Applications 5VSBY 1 21 DRIVE3 Single and Dual Channel DDR Memory Power Systems in S3 2 20 FB3 ACPI Compliant PCs 3 19 P12V PWM4 Graphics Cards - GPU and Memory Supplies GND GND 4 18 FB4 ASIC Power Supplies 29 5 17 Embedded Processor and I/O Supplies DDR VTT COMP4 DSP Supplies DDR VTT 6 16 COMP VDDQ 7 15 FB 89 10 11 12 13 14 FN9143 Rev 5.00 Page 1 of 16 Jul 18, 2007 VDDQ LGATE DDR VTTSNS GND DRIVE2 UGATE FB2 BOOT VIDPGD PHASE VREF OUT S5 VREF IN OCSETISL6537A Ordering Information TEMPERATURE PKG. PART NUMBER PART MARKING RANGE (C) PACKAGE DWG. ISL6537ACR ISL6537ACR 0 to +70 28 Ld 6x6 QFN L28.6x6 ISL6537ACRZ (Note) ISL6537ACRZ 0 to +70 28 Ld 6x6 QFN (Pb-free) L28.6x6 ISL6537ACRZA (Note) ISL6537ACRZ 0 to +70 28 Ld 6x6 QFN (Pb-free) L28.6x6 *Add -T suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN9143 Rev 5.00 Page 2 of 16 Jul 18, 2007