ISL6530 Data Sheet November 15, 2004 FN9052.2 Dual 5V Synchronous Buck Pulse-Width Features Modulator (PWM) Controller for DDRAM Provides V , V , and V voltages for one- and two- DDQ REF TT Memory V and V Termination DDQ TT channel DDRAM memory systems The ISL6530 provides complete control and protection for Excellent voltage regulation dual DC-DC converters optimized for high-performance -V = 2.5V 2% over full operating range DDQ DDRAM memory applications. It is designed to drive low -V = (V 2) 1% over full operating range REF DDQ cost N-channel MOSFETs in synchronous-rectified buck = V 30mV -V TT REF topology to efficiently generate 2.5V V for powering DDQ Supports S3 sleep mode DDRAM memory, V for DDRAM differential signalling, REF and V for signal termination. The ISL6530 integrates all of is held at V 2 via low power window regulator -V TT TT DDQ to minimize wake-up time the control, output adjustment, monitoring and protection functions into a single package. Fast transient response - Full 0% to 100% duty ratio The V output of the converter is maintained at 2.5V DDQ through an integrated precision voltage reference. The V REF Operates from +5V input output is precisely regulated to 1/2 the memory power Overcurrent fault monitor on VDD supply, with a maximum tolerance of 1% over temperature - Does not require extra current sensing element and line voltage variations. V accurately tracks V . TT REF - Uses MOSFETs r During V2 SD sleep mode, the V output is maintained by DS(ON) TT a low power window regulator. Drives inexpensive N-Channel MOSFETs The ISL6530 provides simple, single feedback loop, voltage- Small converter size mode control with fast transient response. It includes two - 300kHz fixed frequency oscillator phase-locked 300kHz triangle-wave oscillators which are o 24 Lead, SOIC or 32 Lead, 5mm 5mm QFN displaced 90 to minimize interference between the two PWM regulators. The regulators feature error amplifiers with Pb-Free Available (RoHS Compliant) a 15MHz gain-bandwidth product and 6V/s slew rate which enables high converter bandwidth for fast transient Applications performance. The resulting PWM duty ratio ranges from 0% V , V , and VREF regulation for DDRAM memory DDQ TT to 100%. systems The ISL6530 protects against over-current conditions by - Main Memory in AMD Athlon and K8, Pentium III, Pentium IV, Transmeta, PowerPC, AlphaPC, and inhibiting PWM operation. The ISL6530 monitors the current UltraSparc based computer systems in the V regulator by using the r of the upper DDQ DS(ON) - Video memory in graphics systems MOSFET which eliminates the need for a current sensing resistor. High-power tracking DC-DC regulators Ordering Information TEMP PKG. o PART NUMBER RANGE( C) PACKAGE DWG. ISL6530CB* 0 to 70 24 Lead SOIC M24.3 ISL6530CBZ* 0 to 70 24 Lead SOIC M24.3 (See Note) (Pb-free) ISL6530CR* 0 to 70 32 Lead 5x5 QFN L32.5x5 ISL6530CRZ* 0 to 70 32 Lead 5x5 QFN L32.5x5 (See Note) (Pb-free) ISL6530EVAL1, 2 Evaluation Board * Add -T suffix for tape and reel option. NOTE: Intersil Pb-free products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 321-724-7143 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.ISL6530 Pinouts 24 LEAD (SOIC) 32 LEAD (QFN) TOP VIEW TOP VIEW 24 UGATE1 1 PGND1 23 LGATE1 BOOT1 2 22 PHASE1 3 PVCC1 32 31 30 29 28 27 26 25 21 VREF 4 OCSET/SD PHASE 1 PVCC1 1 24 20 FB1 5 V2 SD VREF 2 23 OCSET/SD 19 6 PGOOD COMP1 18 FB1 V2 SD SENSE1 7 COMP2 3 22 17 VREF IN 8 SENSE2 COMP1 PGOOD 4 21 16 GNDA 9 FB2 SENSE1 5 20 COMP2 15 PHASE2 10 VCC 14 BOOT2 11 LGATE2 VREF IN SENSE2 6 19 13 UGATE2 12 PGND2 GNDA 7 18 FB2 GNDA VCC 8 17 910 11 12 13 14 15 16 FN9052.2 2 November 15, 2004 PHASE2 BOOT1 BOOT2 BOOT1 BOOT2 UGATE1 UGATE2 UGATE1 PGND2 PGND1 PGND2 PGND1 LGATE2 LGATE1 VCC PVCC1