USERS MANUAL ISL85005DEMO1Z, ISL85005ADEMO1Z UG110 Rev.0.00 Demonstration Boards User Guide Feb 6, 2017 Description Key Features The ISL85005 and ISL85005A are 4.5V to 18V input, 5A Switch selectable EN (enabled/disabled) synchronous buck regulators for applications with input Selectable mode (DEM/Forced CCM) (ISL85005DEMO1Z) voltage from multi-cell batteries or regulated 5V and 12V Internal and external compensation options power rails. These devices also provide an integrated bootstrap diode for the high-side gate driver to reduce the external parts Frequency synchronization option (ISL85005DEMO1Z) count. The ISL85005DEMO1Z and ISL85005ADEMO1Z Adjustable soft-start option (ISL85005ADEMO1Z) platforms allow quick demonstration of the high performance Small and compact design features of the ISL85005 and ISL85005A buck regulators. Related Literature Specifications For a full list of related documents please visit our website These boards have been configured and optimized for the - ISL85005 and ISL85005A product pages following operating conditions: Input voltage ranges from 7V to 15V Ordering Information 5V nominal output voltage PART NUMBER DESCRIPTION Up to 5A output current capability Default internally set 500kHz switching frequency ISL85005DEMO1Z Small form-factor demonstration board for ISL85005FRZ Default internally set 2.3ms soft-start ISL85005ADEMO1Z Small form-factor demonstration board for Operating temperature range: -40C to +85C ISL85005AFRZ GND = DEM C ISL85005A SS ISL85005 VCC = FCCM 1 BOOT 12 SS MODE SYNC/ BOOT C 1 12 4 C MODE 4 VDD PG 2 PG 11 VDD PG 2 11 V PG IN V IN VIN EN 3 EN 10 VIN EN 3 EN 10 PGND PGND VIN 4 FB 9 C VIN 3 C C 4 9 C 5 6 FB R 3 C C 1 R 5 6 2 R 1 R PHASE 2 5 COMP 8 PHASE 5 COMP 8 V OUT C V 1 OUT C AGND PHASE 1 6 7 AGND PHASE 6 7 L 1 L 1 C C 8 9 C C 8 9 FIGURE 1B. ISL85005ADEMO1Z FIGURE 1A. ISL85005DEMO1Z FIGURE 1. BLOCK DIAGRAM UG110 Rev.0.00 Page 1 of 6 Feb 6, 2017ISL85005DEMO1Z, ISL85005ADEMO1Z Connector and Selection Jumper Frequency Synchronization Descriptions (ISL85005DEMO1Z) The ISL85005DEMO1Z and ISL85005ADEMO1Z demonstration The ISL85005 can be synchronized to an external clock with boards include I/O connectors and a selection jumper as shown frequency ranges from 300kHz to 2MHz by applying the external . in Table 1 clock to the SYNC/MODE pin on the ISL85005DEMO1Z demonstration board. The external clock should meet the TABLE 1. CONNECTORS AND JUMPER specifications of the pulse width and voltage level described in REFERENCE the datasheet. DESIGNATOR DESCRIPTION Adjusting Soft-Start Time J1 Selection Jumper for Enable (EN) (ISL85005ADEMO1Z) J3 Input voltage positive connection J4 Input voltage return connection With the SS pin floating, the ISL85005A features an internally set 2.3ms of soft-start time. The soft-start time can be set to a J5 Output voltage positive connection desired value by connecting an external capacitor (C on the SS J6 Output voltage return connection ISL85005ADEMO1Z demonstration board) between the SS pin : and AGND. The capacitance can be calculated by Equation 1 Quick Setup Guide (EQ. 1) C nF = 3.5 t ms 1.6nF SS SS Refer to the following Quick Setup Guide to configure and power-up the board for proper operation. Evaluating Other Output 1. Set the power supply voltage to 12V, and turn off the power Voltages supply. Connect the positive output of power supply to J3 (VIN) and the negative output to J4 (GND). Both ISL85005DEMO1Z and ISL85005ADEMO1Z have a nominal 2. Connect an electronic load to J5 (VOUT) for the positive 5V output voltage. The output voltages are programmable by an connection and J6 (GND) for the negative connection. external resistor divider formed by R and R as shown in 1 2 Figure 1 on page 1. R is usually chosen first, then the value for 3. Measure the output voltage (J5 and J6) with the voltmeter. 1 R can be calculated based on R and the desired output voltage 2 1 4. Place scope probes on VOUT and other test points of interest. using Equation 2. 5. Set EN jumper (J1) to ON position. R 0.8V 1 6. Set the load current to be 0.1A and turn on the power supply, (EQ. 2) ---------------------------------- R = 2 V 0.8V OUT the output voltage should be in regulation with a nominal 5V output. 7. Slowly increase the load up to 5A while monitoring the output PCB Layout Considerations voltage which should remain in regulation with a nominal 5V The PCB layout is critical for proper operation of the ISL85005 output. and ISL85005A. The following guidelines should be followed to 8. Slowly sweep VIN from 7V to 15V, the output voltage should achieve good performance. remain in regulation with a nominal 5V output. 1. Use a multilayer PCB structure to achieve optimized 9. Decrease the input voltage to 0V to shut down the regulator. performance, a four-layer PCB is recommended for this design. Operation Mode Selection 2. Use a combination of bulk capacitors and smaller ceramic (ISL85005DEMO1Z) capacitors with lower ESL for the input capacitors and place them as close to the IC as possible. The ISL85005DEMO1Z can be configured in either forced 3. Place the VDD decoupling capacitor close to the IC between Continuous Conduction Mode (CCM) or Diode Emulation Mode VDD and GND. A 1F ceramic capacitor is typically used. (DEM): 4. Place a bootstrap capacitor close to the IC between the BOOT In the default configuration of ISL85005DEMO1Z, and PHASE pins. A 0.1F ceramic capacitor is typically used. SYNC/MODE (Pin 1) of ISL85005 is floating, the ISL85005 5. Connect the feedback resistor divider between the output operates in forced CCM. capacitor positive terminal and the AGND pin of the IC, and To configure the ISL85005 in DEM, short the SYNC/MODE pin place the resistors close to the FB pin of the IC. to GND by populating a 0 resistor for C . DEM enables SS 6. Connect the EPAD of the IC to the GND planes underneath automatic transition from CCM to DCM and higher efficiency at using multiple thermal vias to improve thermal performance. light-load conditions. UG110 Rev.0.00 Page 2 of 6 Feb 6, 2017