High Speed, Dual Channel, 6A, Power MOSFET Driver With Programmable Delays ISL89166, ISL89167, ISL89168 Features Typical ON-resistance <1 The ISL89166, ISL89167, and ISL89168 are high-speed, 6A, dual channel MOSFET drivers. These parts are similar to the Specified Miller plateau drive currents ISL89160, ISL89161, ISL89162 drivers but use the NC pins for Very low thermal impedance ( = 3C/W) JC programming the rising edge time delays of the outputs used for dead time control. Hysteretic Input logic levels for 3.3V CMOS, 5V CMOS, and TTL Precision threshold inputs for optional time delays with As an alternative to using external RC circuits for time delays, the external RC components programmable delays on the RDTA and RDTB pins allows the user to delay the rising edge of the respective outputs just by Instead of RC components for time delays, a resistor can be connecting an appropriate resistor value between these pins and used to program delays ground. The accuracy and temperature characteristics of the 20ns rise and fall time driving a 10nF load. time delays are specified freeing the user of the need to select NC pins may be connected to ground or VDD for flexible PCB appropriate external resistors and capacitors that traditionally layout options are applied to the logic inputs to delay the output edges. At high switching frequencies, these MOSFET drivers use very Applications little internal bias currents. Separate, non-overlapping drive Synchronous Rectifier (SR) Driver circuits are used to drive each CMOS output FET to prevent shoot-thru currents in the output stage. Switch mode power supplies Motor Drives, Class D amplifiers, UPS, Inverters The start-up sequence is design to prevent unexpected glitches when V is being turned on or turned off. When V < ~1V, an DD DD Pulse Transformer Driver internal 10k resistor between the output and ground helps to Clock/Line Driver keep the output voltage low. When ~1V <V < UV, both outputs DD are driven low with very low resistance and the logic inputs are ignored. This insures that the driven FETs are off. When V > UVLO, and after a short delay, the outputs now respond to DD the logic inputs. 350 V DD 300 +125C (WORST CASE) RDTA RDTB 250 8 1 INA OUTA 200 2 7 EPAD GND 3 6 150 INB +25C (TYPICAL) OUTB 4 5 100 4.7F 50 -40C (WORST CASE) 0 0 5 10 15 20 RDT (2k to 20k) FIGURE 1. TYPICAL APPLICATION FIGURE 2. PROGRAMMABLE TIME DELAYS February 26, 2013 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Copyright Intersil Americas LLC 2011-2013. All Rights Reserved FN7720.2 Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. DELAY (ns)ISL89166, ISL89167, ISL89168 Block Diagram V DD Separate FET drives, with The UV comparator holds off For clarity, only one non-overlapping outputs, the outputs until V ~> DD prevent shoot-thru channel is shown 3.3VDC. currents in the output CMOS FETs resulting with very low operating RDTx currents. RDTx ISL89166 rising INx edge OUTx delay 10k ISL89167, EPAD ISL89168 For proper thermal and electrical GND performance, the EPAD must be connected to the PCB ground plane. Pin Configurations Pin Descriptions PIN ISL89166FR, ISL89166FB ISL89167FR, ISL89167FB NUMBER SYMBOL DESCRIPTION (8 LD TDFN, EPSOIC) (8 LD TDFN, EPSOIC) TOP VIEW TOP VIEW 1 RDTA Connect a resistor between this pin and ground to program the rising edge delay of RDTA RDTB RDTA 8 RDTB 1 8 1 OUTA, 0k to 20k INA 2 7 OUTA /INA 2 7 OUTA 2 INA or /INA Channel A input, 0V to VDD GND VDD GND VDD 3 6 3 6 3 GND Power Ground, 0V INB 4 5 OUTB /INB 4 5 OUTB 4 INB or /INB Channel B enable, 0V to VDD 5 OUTB Channel B output 6 VDD Power input, 4.5V to 16V ISL89168FR, ISL89168FB (8 LD TDFN, EPSOIC) 7 OUTA Channel A output, 0V to VDD TOP VIEW 8 RDTB Connect a resistor between this pin and ground to program the rising edge delay of RDTA 1 8 RDTB OUTB, 0k to 20k /INA OUTA 2 7 EPAD Power Ground, 0V GND 3 6 VDD INB OUTB 4 5 FN7720.2 2 February 26, 2013