DATASHEET ISLA212P50 FN7843 Rev 2.00 12-Bit, 500MSPS ADC January 25, 2013 The ISLA212P50 is a 12-bit, 500MSPS analog-to-digital Features converter designed with Intersils proprietary FemtoCharge Automatic fine interleave correction calibration technology on a standard CMOS process. The ISLA212P50 is part of a pin-compatible portfolio of 12 to 16-bit A/Ds with Single supply 1.8V operation maximum sample rates ranging from 130MSPS to 500MSPS. Clock duty cycle stabilizer The device utilizes two time-interleaved 250MSPS unit ADCs to 75f clock jitter achieve the ultimate sample rate of 500MSPS. A single 700MHz bandwidth 500MHz conversion clock is presented to the converter, and all interleave clocking is managed internally. The proprietary Programmable built-in test patterns Intersil Interleave Engine (I2E) performs automatic correction Multi-ADC support of offset, gain, and sample time mismatches between the unit - SPI programmable fine gain and offset control ADCs to optimize performance. - Support for multiple ADC synchronization A serial peripheral interface (SPI) port allows for extensive - Optimized output timing configurability of the A/D. The SPI also controls the interleave Nap and sleep modes correction circuitry, allowing the system to issue offline and continuous calibration commands as well as configure many - 200s sleep wake-up time dynamic parameters. Data output clock Digital output data is presented in selectable LVDS or CMOS DDR LVDS-compatible or LVCMOS outputs formats. The ISLA212P50 is available in a 72 Ld QFN package Selectable clock divider with an exposed paddle. Operating from a 1.8V supply, performance is specified over the full industrial temperature Applications range (-40C to +85C). Radar array processing Software defined radios Key Specifications Broadband communications SNR 500MSPS - = 70.3dBFS f = 30MHz High-performance data acquisition IN - = 68.7dBFS f = 363MHz IN Communications test equipment SFDR 500MSPS Related Literature -= 84dBc f = 30MHz IN -= 76dBc f = 363MHz See AN1715, Evaluation of Lower Resolution ADCs with IN Total Power Consumption = 823mW 500MSPS Konverter Pin-Compatible Family SPEED MODEL RESOLUTION (MSPS) CLKP CLKOUTP CLOCK ISLA216P25 16 250 MANAGEMENT CLKN CLKOUTN ISLA216P20 16 200 ISLA216P13 16 130 12-BIT D 11:0 P SHA 250 MSPS ADC D 11:0 N ISLA214P50 14 500 VREF ORP VINP Gain, Offset DIGITAL ISLA214P25 14 250 ORN and Skew I2E ERROR Adjustments CORRECTION VINN ISLA214P20 14 200 12-BIT ISLA214P13 14 130 SHA 250 MSPS ADC VREF ISLA212P50 12 500 + VCM SPI ISLA212P25 12 250 CONTROL ISLA212P20 12 200 ISLA212P13 12 130 FN7843 Rev 2.00 Page 1 of 38 January 25, 2013 AVSS AVDD NAPSLP RESETN CLKDIV CLKDIVRSTP CLKDIVRSTN CSB SCLK SDIO SDO RLVDS OVSS OVDDISLA212P50 Pin Configuration- LVDS MODE ISLA212P50 (72 LD QFN) TOP VIEW 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 DNC 1 54 D1P DNC D1N 2 53 NAPSLP 3 52 D2P VCM 4 51 D2N 5 50 AVSS D3P AVDD 6 49 D3N AVSS 7 48 CLKOUTP VINN 8 47 CLKOUTN 9 46 VINN RLVDS VINP 10 45 OVSS VINP D4P 11 44 AVSS 12 43 D4N AVDD 13 42 D5P AVSS 14 41 D5N CLKDIV D6P 15 40 IPTAT 16 39 D6N Thermal Pad Not Drawn to Scale, Consult Mechanical Drawing DNC 17 38 D7P for Physical Dimensions Connect Thermal Pad to AVSS RESETN 18 37 D7N 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Descriptions - 72 Ld QFN, LVDS Mode PIN NUMBER LVDS PIN NAME LVDS PIN FUNCTION 1, 2, 17, 57, 58, 59, 60 DNC Do Not Connect 6, 13, 19, 20, 21, 70, 71, 72 AVDD 1.8V Analog Supply 5, 7, 12, 14 AVSS Analog Ground 27, 32, 62 OVDD 1.8V Output Supply 26, 45, 61, 65 OVSS Output Ground 3 NAPSLP Tri-Level Power Control (Nap, Sleep modes) 4 VCM Common Mode Output 8, 9 VINN Analog Input Negative FN7843 Rev 2.00 Page 2 of 38 January 25, 2013 AVDD AVDD AVDD AVDD AVDD AVDD CLKP SDIO CLKN SCLK CLKDIVRSTP CSB CLKDIVRSTN SDO OVSS OVSS OVDD ORP D11N ORN D11P OVDD D10N OVSS D10P DNC OVDD DNC D9N DNC D9P DNC D8N D0P D8P D0N