LV810RILFT Renesas

DATASHEET BUFFER/CLOCK DRIVER ICSLV810 Description Features The ICSLV810 is a low skew 1.5 V to 2.5 V, 1:10 fanout Packaged in 20-pin QSOP/SSOP buffer. This device is specifically designed for data Split 1:10 fanout Buffer communications clock management. The large fanout from Maximum skew between outputs of different packages a single input line reduces loading on the input clock. The 0.75 ns TTL level outputs reduce noise levels on the part. Typical Max propagation delay of 3.8 ns applications are clock and signal distribution. Operating voltage of 1.5 V to 2.5 V on Bank A Operating voltage of 1.5 V to 2.5 V on Banks B and C Advanced, low power, CMOS process Industrial temperature range -40 C to +85 C 3.3 V tolerant input when VDDA=2.5 V Pb (lead) free packaging Block Diagram VDDA CLK 1 CLK 2 CLK 3 CLK 4 CLK 5 CLKIN CLK 6 CLK 7 CLK 8 CLK 9 CLK 10 VDDB VDDC IDT / ICS BUFFER/CLOCK DRIVER 1 ICSLV810 REV H 051310ICSLV810 BUFFER/CLOCK DRIVER FAN OUT BUFFER Pin Assignment 1 20 CLKIN VDDB 2 19 GND CLK 10 3 18 CLK 1 CLK 9 4 17 VDDA GND 16 CLK 2 5 CLK 8 15 GND VDDC 6 7 CLK 3 14 CLK 7 8 VDDA 13 GND 9 12 CLK 4 CLK 6 10 GND 11 CLK 5 20 pin (150mil) SSOP Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 CLKIN Input Clock input. 2 GND Power Connect to ground. 3 CLK1 Output Clock output. 4 VDDA Power Connect to +1.5 - +2.5 V. 5 CLK2 Output Clock output. 6 GND Power Connect to ground. 7 CLK3 Output Clock output. 8 VDDA Power Connect to +1.5 - +2.5 V. 9 CLK4 Output Clock output. 10 GND Power Connect to ground. 11 CLK5 Output Clock output. 12 CLK6 Output Clock output. 13 GND Power Connect to ground. 14 CLK7 Output Clock output. 15 VDDC Power Connect to +1.5 - 2.5 V. 16 CLK8 Output Clock output. 17 GND Power Connect to ground. 18 CLK9 Output Clock output. 19 CLK10 Output Clock output. 20 VDDB Power Connect to +1.5 - 2.5 V. IDT / ICS BUFFER/CLOCK DRIVER 2 ICSLV810 REV H 051310