DATASHEET ZERO DELAY, LOW SKEW BUFFER MK2304-1 Description Features The MK2304-1 is a low jitter, low skew, high performance Packaged in 8-pin SOIC Phase Lock Loop (PLL) based zero delay buffer for high Zero input-output delay speed applications. Based on IDTs proprietary low jitter 2 banks of two 1X outputs PLL techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The MK2304-1 includes Output to output skew is less than 200 ps two banks of two outputs each 1X. In the zero delay mode, Output clocks up to 133 MHz at 3.3 V the rising edge of the input clock is aligned with the rising Full CMOS outputs with 8 mA output drive capability at edges of all 4 outputs. Compared to competitive CMOS TTL levels at 3.3 V devices, the MK2304-1 has the lowest jitter. TM Spread Smart technology Works with Spread IDT manufactures the largest variety of clock generators Spectrum clock generators and buffers and is the largest clock supplier in the world. Advanced, low power, sub micron CMOS process Operating voltage of 3.3 V Available in industrial temperature range Block Diagram VDD 1 FBIN CLKA1 PLL BANK CLKIN A CLKA2 CLKB1 BANK B CLKB2 1 GND IDT ZERO DELAY, LOW SKEW BUFFER 1 MK2304-1 REV G 072710MK2304-1 ZERO DELAY, LOW SKEW BUFFER ZDB Pin Assignment Feedback Configuration Table Feedback From CLKA1:A2 CLKB1:B2 Bank A CLKIN CLKIN Bank B CLKIN CLKIN REF 8 1 FBK CLKA1 2 7 VDD CLKA2 3 6 CLKB2 GND 5 4 CLKB1 8 Pin (150 mil) SOIC Pin Descriptions Pin Pin Name Pin Type Pin Description Number 1 REF Input Clock input. Connect to input clock source. 5 V tolerant input. 2 CLKA1 Output Clock A1 output. 3 CLKA2 Output Clock A2 output. 4 GND Power Connect to ground. 5 CLKB1 Output Clock B1 output. 6 CLKB1 Output Clock B2 output. 7 VDD Power 3.3 V Power Supply. 8 FBK Input PLL feedback input. IDT ZERO DELAY, LOW SKEW BUFFER 2 MK2304-1 REV G 072710