DATASHEET ZERO DELAY, LOW SKEW BUFFER MK2304-2 Description Features The MK2304-2 is a low jitter, low skew, high performance Packaged in 8 pin SOIC Phase Lock Loop (PLL) based zero delay buffer for high Zero input-output delay speed applications. Based on IDTs proprietary low jitter Two 1X outputs plus two 1/2X outputs PLL techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The MK2304-2 includes Output to output skew is less than 200 ps a bank of two outputs running at 1/2X. In the zero delay Output clocks up from 10 MHz to 133 MHz at 3.3 V mode, the rising edge of the input clock is aligned with the Ability to generate 2X the input rising edges of all 4 outputs. Compared to competitive CMOS devices, the MK2304-2 has the lowest jitter. Full CMOS outputs with 8 mA output drive capability at TTL levels at 3.3 V The MK2304-2 PLL enters a power-down state when there TM Spread Smart technology works with spread spectrum are no rising edges on the REF input. In this mode, all clock generators outputs are tri-stated and the PLL is turned off, resulting in Advanced, low power, sub micron CMOS process leass than 25 A of current draw. Operating voltage of 3.3 V IDT manufactures the largest variety of clock generators Available in industial temperature operation and buffers and is the largest clock supplier in the world. Pb (lead) free package Low Standby Current Block Diagram VDD 1 FBIN CLKA1 PLL BANK CLKIN A CLKA2 CLKB1 BANK /2 B CLKB2 1 GND IDT ZERO DELAY, LOW SKEW BUFFER 1 MK2304-2 REV G 051310MK2304-2 ZERO DELAY, LOW SKEW BUFFER ZDB Pin Assignment Feedback Configuration Table Feedback From CLKA1:A2 CLKB1:B2 Bank A CLKIN CLKIN/2 Bank B 2XCLKIN CLKIN REF 8 1 FBK CLKA1 2 7 VDD CLKA2 3 6 CLKB2 GND 5 4 CLKB1 8 Pin (150 mil) SOIC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 REF Input Clock input. Connect to input clock source, 5 V tolerant input. 2 CLKA1 Output Clock A1 output. 3 CLKA2 Output Clock A2 output. 4 GND Power Connect to ground. 5 CLKB1 Output Clock B1 output. 6 CLKB1 Output Clock B2 output. 7 VDD Power 3.3V Power Supply. 8 FBK Input PLL feedback input External Components The Mk2304-2 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.1F should be connected between VDD and GND, as close to the part as possible. A 33 series terminating resistor should be used on each clock output to reduce reflections. IDT ZERO DELAY, LOW SKEW BUFFER 2 MK2304-2 REV G 051310