DATASHEET 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER MK2308-1H Description Features The MK2308-1H is a low phase noise, high-speed PLL Clock outputs from 10 to 133 MHz based, 8-output, low skew zero delay buffer. Based on ICS Zero input-output delay proprietary low jitter Phase Locked Loop (PLL) techniques, Eight low skew (<200 ps) outputs the device provides eight low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the Device-to-device skew <700 ps PLL (for zero delay), or directly from the input (for testing), Full CMOS outputs with 25 mA output drive capability at and can be set to tri-state mode or to stop at a low level. For TTL levels normal operation as a zero delay buffer, any output clock is 5 V tolerant FBIN and CLKIN pins tied to the FBIN pin. Tri-state mode for board-level testing ICS manufactures a large variety of clock generators and Advanced, low-power, sub-micron CMOS process buffers. Operating voltage of 3.3 V Industrial temperature range available Packaged in 16-pin SOIC and TSSOP packages Available in Pb (lead) free package Industrial and commercial temp operation Block Diagram VDD 2 Control 2 S2, S1 CLKA1 Logic CLKA2 CLKA3 CLKIN CLKA4 1 Clock Synthesis FBIN PLL 0 CLKB1 CLKB2 CLKB3 CLKB4 2 Feedback is shown from CLKB4 for GND illustration, but may come from any output. IDT / ICS 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER 1 MK2308-1H REV D 081505MK2308-1H 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER ZDB Pin Assignment CLKIN 1 16 FBIN CLKA1 2 15 CLKA4 CLKA2 3 14 CLKA3 VDD 4 13 VDD GND 5 12 GND CLKB1 6 11 CLKB4 CLKB2 7 10 CLKB3 S2 8 9 S1 16-pin narrow (150 mil) SOIC and (173 mil) TSSOP Output Clock Mode Select Table S2 S1 CLKA1:A4 CLKB1:B4 A & B Source PLL Status 0 0 Tri-state (note 1) Tri-state (note 1) PLL OFF 0 1 Running Tri-state (note 1) PLL ON 1 0 Running Running CLKIN (note 2) OFF 1 1 Running Running PLL ON Note 1. Outputs are in high impedance state Note 2. Buffer mode only not zero delay between input and output Pin Descriptions Pin Pin Pin Type Pin Description Number Name 1 CLKIN Input Clock input (5 V tolerant). 2 - 3 CLKA1:A4 Output Clock outputs A1:A4. See table above. 4 VDD Power Power supply. Connect to 3.3 V. 5 GND Power Connect to ground. 6 - 7 CLKB1:B4 Output Clock outputs B1:B4. See table above. 8 S2 Input Select input 2. See table above. Internal pull-up. 9 S1 Input Select input 1. See table above. Internal pull-up. 10 - 11 CLKB1:B4 Output Clock outputs B1:B4. See table above. 12 GND Power Connect to ground. 13 VDD Power Power supply. Connect to 3.3 V. 14 - 15 CLKA1:A4 Output Clock outputs A1:A4. See table above. 16 FBIN Input Feedback input. Connect to any output under normal operation (5 V tolerant). IDT / ICS 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER 2 MK2308-1H REV D 081505