DATASHEET ZERO DELAY, LOW SKEW BUFFER MK2308-2 Description Features The MK2308-2 is a low jitter, low skew, high performance Packaged in 16-pin SOIC Phase-Lock Loop (PLL) based zero delay buffer for high Pb (lead) free package speed applications. Based on IDTs proprietary low jitter Zero input-output delay PLL techniques, the device provides eight low skew outputs at speeds up to 133.3 MHz at 3.3 V. The MK2308-2 Four 1X outputs plus four 1/2X outputs includes a bank of four outputs running at 1/2X. In the zero Output to output skew is less than 250 ps delay mode, the rising edge of the input clock is aligned Output clocks up to 133.3 MHz at 3.3 V with the rising edges of all eight outputs. Compared to competitive CMOS devices, the MK2308-2 has the lowest Ability to generate 2X the input jitter. Full CMOS outputs with 18 mA output drive capability at TTL levels at 3.3 V TM Spread Smart technology works with spread spectrum clock generators Advanced, low power, sub micron CMOS process Operating voltage of 3.3 V Block Diagram VDD 2 CLKA1 FBIN CLKA2 PLL BANK CLKIN A CLKA3 CLKA4 /2 CLKB1 CLKB2 BANK Control 2 S2, S1 B Logic CLKB3 CLKB4 2 GND IDT ZERO DELAY, LOW SKEW BUFFER 1 MK2308-2 REV E 051310MK2308-2 ZERO DELAY, LOW SKEW BUFFER ZDB Pin Assignment Feedback Configuration Table Feedback From CLKA1:A4 CLKB1:B4 CLKIN 1 16 FBIN Bank A CLKIN CLKIN/2 CLKA1 2 CLKA4 15 Bank B 2XCLKIN CLKIN CLKA2 3 14 CLKA3 VDD 4 13 VDD GND 5 12 GND CLKB1 6 11 CLKB4 CLKB2 7 10 CLKB3 S2 8 9 S1 16-pin (150 mil) SOIC Output Clock Mode Select Table S2 S1 Clocks A1:A4 Clocks B1:B4 Internet Generation PLL Status 0 0 Tri-state (high impedance) Tri-state (high impedance) None On 0 1 Running Tri-state (high impedance) PLL On 1 0 Running Running Buffer only (no zero delay) Off 1 1 Running Running PLL On Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 CLKIN Input Clock input. Connect to input clock source. 2 - 3 CLKA1:A4 Output Clock A bank of four outputs. 4 VDD Power Power supply. Connect pin to same voltage as pin 13 (either 3.3 V ). 5 GND Power Connect to ground. 6 - 7 CLKB1:B4 Output Clock B bank of four outputs. These are low skew divide by two of bank A. 8 S2 Input Select input 2. Selects mode for outputs per table above. 9 S1 Input Select input 1. Selects mode for outputs per table above. 10 - 11 CLKB1:B4 Output Clock B bank of four outputs. These are low skew divide by two of bank A. 12 GND Power Connect to ground. 13 VDD Power Power supply. Connect pin to same voltage as pin 4 (either 3.3 V ). 14 - 15 CLKA1:A4 Output Clock A bank of four outputs. 16 FBIN Input Feedback input. Determines outputs per table above. IDT ZERO DELAY, LOW SKEW BUFFER 2 MK2308-2 REV E 051310