Preliminary Datasheet
Specifications in this document are tentative and subject to change.
RX111 Group
R01DS0190EJ0060
Renesas MCUs
Rev.0.60
Apr 15, 2013
32 MHz 32-bit RX MCUs, 50 DMIPS,
up to 128 Kbytes of flash memory, USB 2.0 full-speed host/function/
OTG up to 5 comms channels, 12-bit A/D, 8-bit D/A, RTC
Features
PLQP0064KB-A 10 10 mm, 0.5 mm pitch
32-bit RX CPU core
PLQP0064GA-A 14 14 mm, 0.8 mm pitch
PLQP0048KB-A 7 7 mm, 0.5 mm pitch
32 MHz maximum operating frequency
Capable of 49 DMIPS when operating at 32 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32-bit 32-bit operations
Multiplication and division unit handles 32-bit 32-bit
PWQN0048KB-A 7 7mm, 0.50mm pitch
operations (multiplication instructions take one CPU
PWQN0040KC-A 6 6mm, 0.50mm pitch
clock cycle)
Fast interrupt
PWLG0064KA-A 5 5mm, 0.5mm pitch
CISC Harvard architecture with 5-stage pipeline
PWLG0036KA-A 4 4 mm, 0.5 mm pitch
Variable-length instructions, ultra-compact code
On-chip debugging circuit
Independent watchdog timer (IWDT)
Low power consumption function
15-kHz on-chip oscillator produces a dedicated clock
Operation from a single 1.8 to 3.6 V supply
signal to drive IWDT operation.
Three low power consumption modes
On-chip functions for IEC 60730 compliance
On-chip flash memory for code, no wait states
Clock frequency accuracy measurement circuit, IWDT,
Operation at 32 MHz, read cycle of 31.25 ns
functions to assist in RAM testing, etc.
No wait states for reading at full CPU speed
USB
16 to 128 Kbyte capacities
USB2.0 host (32-Kbyte or more ROM)/function/
Programmable at 1.8 V
OTG (On-The-Go) (one channel)
For instructions and operands
Full-speed = 12 Mbps, low-speed = 1.5 Mbps
On-chip data flash memory
Isochronous transfer
8 Kbytes
BC (Battery Charging)
1,000,000 Erase/Write cycles
Up to five channels for communication
BGO (Background Operation)
SCI: Asynchronous mode, clock synchronous mode,
On-chip SRAM, no wait states
smart card interface (up to seven channels)
8 to 16 Kbyte capacities
2
I C bus interface: Transfer at up to 400 kbps, capable of
Data transfer controller (DTC) SMBus operation (one channel)
Four transfer modes
RSPI (one channel)
Transfer can be set for each interrupt source.
Up to 8 extended-function timers
Event link controller (ELC) 16-bit MTU: Input capture/output compare,
Module operation can be initiated by event signals
complementary PWM output, phase counting mode
without going through interrupts.
(six channels)
Link operation between modules is possible while the
16-bit CMT (two channels)
CPU is sleeping.
12-bit A/D converter
Reset and power supply voltage management Up to 14 channels
Six types including Power-On Reset (POR)
1 s minimum conversion speed
Low voltage detection (LVD) with voltage settings
Double trigger (data duplication) function for motor
control
Clock functions
External clock input frequency: Up to 20 MHz
8-bit D/A converter
Main oscillator frequency: 1 to 20 MHz
Two channels (for 64 pins only)
Sub-clock oscillator frequency: 32.768 kHz
Temperature sensor
PLL circuit input: 4 to 8 MHz
Low-speed on-chip oscillator: 4 MHz General I/O ports
High-speed on-chip oscillator: 32 MHz 5-V tolerant, open drain, input pull-up
IWDT-dedicated on-chip oscillator: 15 kHz
Multi-function pin controller (MPC)
Generate a dedicated 32.768-kHz clock for the RTC
Multiple I/O pins can be selected for peripheral functions.
On-chip clock frequency accuracy measurement circuit
Operating temperature range
(CAC)
40 C to 85C
Realtime clock (RTC)
40C to 105C
30-second, leap year, and error adjustment functions
Calendar count mode or binary count mode selectable
Capable of initiating exit from software standby mode
R01DS0190EJ0060 Rev.0.60 Page 1 of 56
Apr 15, 2013Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RX111 Group 1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different
packages.
Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will
differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1 Outline of Specifications (1/3)
Classification Module/Function Description
CPU CPU Maximum operating frequency: 32 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per one clock cycle
Address space: 4-Gbyte linear
Register set
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32-bit 32-bit 64-bit
On-chip divider: 32-bit 32-bit 32 bits
Barrel shifter: 32 bits
Memory ROM Capacity: 16 K /32 K /64 K /96 K /128 Kbytes
32 MHz, no-wait memory access
Programming/erasing method:
Serial programming (asynchronous serial communication/USB communication), self-programming
RAM Capacity: 8 K /10 K /16 Kbytes
32 MHz, no-wait memory access
E2 DataFlash Capacity: 8 Kbytes
Number of erase/write cycles: 1,000,000 (typ)
MCU operating mode Single-chip mode
Clock Clock generation circuit Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
IWDT-dedicated on-chip oscillator, and PLL frequency synthesizer
Oscillation stop detection: Available
Measurement circuit for accuracy of clock frequency (clock accuracy check: CAC)
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the peripheral module clock (PCLK): 32 MHz (at
max.)
The flash peripheral circuit runs in synchronization with the FlashIF clock (FCLK): 32 MHz (at max.)
The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16, 32,
64).
Resets RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
Voltage detection Voltage detection circuit When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
(LVDAa) is generated.
Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
Low power Low power consumption Module stop function
consumption functions Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
Function for lower operating Operating power control modes
power consumption High-speed operating mode, middle-speed operating mode, and low-speed operating mode
Interrupt Interrupt controller (ICUb) Interrupt vectors: 82
External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
Non-maskable interrupts: 4 (NMI pin, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt,
and IWDT interrupt)
16 levels specifiable for the order of priority
R01DS0190EJ0060 Rev.0.60 Page 2 of 56
Apr 15, 2013